diff options
Diffstat (limited to 'src/cpu/intel/ep80579')
| -rw-r--r-- | src/cpu/intel/ep80579/Kconfig | 1 | ||||
| -rw-r--r-- | src/cpu/intel/ep80579/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/cpu/intel/ep80579/ep80579_init.c | 10 | ||||
| -rw-r--r-- | src/cpu/intel/ep80579/microcode_blob.c | 13 |
4 files changed, 16 insertions, 9 deletions
diff --git a/src/cpu/intel/ep80579/Kconfig b/src/cpu/intel/ep80579/Kconfig index 025ad3f81e..380869a610 100644 --- a/src/cpu/intel/ep80579/Kconfig +++ b/src/cpu/intel/ep80579/Kconfig @@ -1,3 +1,4 @@ config CPU_INTEL_EP80579 bool select SSE + select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/ep80579/Makefile.inc b/src/cpu/intel/ep80579/Makefile.inc index 080e2eec9c..b213c08c1e 100644 --- a/src/cpu/intel/ep80579/Makefile.inc +++ b/src/cpu/intel/ep80579/Makefile.inc @@ -7,3 +7,4 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm subdirs-y += ../microcode +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/cpu/intel/ep80579/ep80579_init.c b/src/cpu/intel/ep80579/ep80579_init.c index b1c1e22be0..22166b16ca 100644 --- a/src/cpu/intel/ep80579/ep80579_init.c +++ b/src/cpu/intel/ep80579/ep80579_init.c @@ -29,14 +29,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> -static u32 microcode_updates[] = { - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, -}; - static void ep80579_init(device_t dev) { /* Turn on caching if we haven't already */ @@ -45,7 +37,7 @@ static void ep80579_init(device_t dev) x86_mtrr_check(); /* Update the microcode */ - intel_update_microcode(microcode_updates); + intel_update_microcode_from_cbfs(); /* Enable the local cpu apics */ setup_lapic(); diff --git a/src/cpu/intel/ep80579/microcode_blob.c b/src/cpu/intel/ep80579/microcode_blob.c new file mode 100644 index 0000000000..cb95b1ae71 --- /dev/null +++ b/src/cpu/intel/ep80579/microcode_blob.c @@ -0,0 +1,13 @@ +/* + * We support updating microcode from CBFS, but do not have any microcode + * updates for this CPU. This will generate a useless cpu_microcode_blob.bin in + * CBFS, but this file can be later replaced without needing to recompile the + * coreboot.rom image. + */ +unsigned microcode_updates_ep80579[] = { + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; |