diff options
Diffstat (limited to 'src/cpu/intel/car/p3')
| -rw-r--r-- | src/cpu/intel/car/p3/cache_as_ram.S | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 1431d323e6..779dbcca8a 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -42,7 +42,7 @@ clear_var_mtrr: inc %ecx dec %ebx jnz clear_var_mtrr - post_code(POST_SOC_SET_DEF_MTRR_TYPE) + post_code(POSTCODE_SOC_SET_DEF_MTRR_TYPE) /* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -50,7 +50,7 @@ clear_var_mtrr: andl $(~0x00000cff), %eax wrmsr - post_code(POST_SOC_DETERMINE_CPU_ADDR_BITS) + post_code(POSTCODE_SOC_DETERMINE_CPU_ADDR_BITS) /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ movl $1, %eax @@ -68,7 +68,7 @@ addrsize_set_high: movl $MTRR_PHYS_MASK(1), %ecx wrmsr - post_code(POST_SOC_SET_CAR_BASE) + post_code(POSTCODE_SOC_SET_CAR_BASE) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx @@ -84,7 +84,7 @@ addrsize_set_high: orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(POST_SOC_ENABLE_MTRRS) + post_code(POSTCODE_SOC_ENABLE_MTRRS) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -92,7 +92,7 @@ addrsize_set_high: orl $MTRR_DEF_TYPE_EN, %eax wrmsr - post_code(POST_SOC_ENABLE_CACHE) + post_code(POSTCODE_SOC_ENABLE_CACHE) /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax @@ -114,7 +114,7 @@ addrsize_set_high: xorl %eax, %eax rep stosl - post_code(POST_SOC_DISABLE_CACHE) + post_code(POSTCODE_SOC_DISABLE_CACHE) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -133,7 +133,7 @@ addrsize_set_high: orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(POST_SOC_FILL_CACHE) + post_code(POSTCODE_SOC_FILL_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -156,7 +156,7 @@ addrsize_set_high: pushl %eax /* tsc[31:0] */ before_c_entry: - post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) + post_code(POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY) call bootblock_c_entry_bist /* Should never see this postcode */ |