diff options
| author | Yuchen He <yuchenhe126@gmail.com> | 2023-07-25 21:28:36 +0200 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-08-05 16:04:46 +0000 |
| commit | 1e67adbc73e30be098ce163e3d27a7a7ecf68ae0 (patch) | |
| tree | a2880851ac6c754d94fc056472beb5ec133ab0b4 /src/cpu/intel/car/p3 | |
| parent | 71b8ee0da407158d51eb7d86a6e1d4c458fc8e96 (diff) | |
src/*/post_code.h: Change post code prefix to POSTCODE
The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.
The files was changed by running the following bash script from the
top level directory.
header="src/soc/amd/common/block/include/amdblocks/post_codes.h \
src/include/cpu/intel/post_codes.h \
src/soc/intel/common/block/include/intelblocks/post_codes.h"
array=`grep -r "#define POST_" $header | \
tr '\t' ' ' | cut -d ":" -f 2 | cut -d " " -f 2`
for str in $array; do
splitstr=`echo $str | cut -d '_' -f2-`
grep -r $str src | cut -d ':' -f 1 | \
xargs sed -i'' -e "s/$str/POSTCODE_$splitstr/g"
done
Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad
Signed-off-by: Yuchen He <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76044
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/cpu/intel/car/p3')
| -rw-r--r-- | src/cpu/intel/car/p3/cache_as_ram.S | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 1431d323e6..779dbcca8a 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -42,7 +42,7 @@ clear_var_mtrr: inc %ecx dec %ebx jnz clear_var_mtrr - post_code(POST_SOC_SET_DEF_MTRR_TYPE) + post_code(POSTCODE_SOC_SET_DEF_MTRR_TYPE) /* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -50,7 +50,7 @@ clear_var_mtrr: andl $(~0x00000cff), %eax wrmsr - post_code(POST_SOC_DETERMINE_CPU_ADDR_BITS) + post_code(POSTCODE_SOC_DETERMINE_CPU_ADDR_BITS) /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ movl $1, %eax @@ -68,7 +68,7 @@ addrsize_set_high: movl $MTRR_PHYS_MASK(1), %ecx wrmsr - post_code(POST_SOC_SET_CAR_BASE) + post_code(POSTCODE_SOC_SET_CAR_BASE) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx @@ -84,7 +84,7 @@ addrsize_set_high: orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(POST_SOC_ENABLE_MTRRS) + post_code(POSTCODE_SOC_ENABLE_MTRRS) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -92,7 +92,7 @@ addrsize_set_high: orl $MTRR_DEF_TYPE_EN, %eax wrmsr - post_code(POST_SOC_ENABLE_CACHE) + post_code(POSTCODE_SOC_ENABLE_CACHE) /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax @@ -114,7 +114,7 @@ addrsize_set_high: xorl %eax, %eax rep stosl - post_code(POST_SOC_DISABLE_CACHE) + post_code(POSTCODE_SOC_DISABLE_CACHE) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -133,7 +133,7 @@ addrsize_set_high: orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(POST_SOC_FILL_CACHE) + post_code(POSTCODE_SOC_FILL_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -156,7 +156,7 @@ addrsize_set_high: pushl %eax /* tsc[31:0] */ before_c_entry: - post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) + post_code(POSTCODE_BOOTBLOCK_BEFORE_C_ENTRY) call bootblock_c_entry_bist /* Should never see this postcode */ |