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path: root/src/cpu/intel/car/cache_as_ram.inc
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Diffstat (limited to 'src/cpu/intel/car/cache_as_ram.inc')
-rw-r--r--src/cpu/intel/car/cache_as_ram.inc12
1 files changed, 3 insertions, 9 deletions
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index 2310d7d9d2..4ad2fce071 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -231,12 +231,6 @@ clear_fixed_var_mtrr_out:
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
-#if CONFIG_TINY_BOOTBLOCK
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
-
/*
* Enable write base caching so we can do execute in place (XIP)
* on the flash ROM.
@@ -244,11 +238,11 @@ clear_fixed_var_mtrr_out:
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
/*
- * IMPORTANT: The two lines below can _not_ be written like this:
- * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+ * IMPORTANT: The following calculation _must_ be done at runtime. See
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl $REAL_XIP_ROM_BASE, %eax
+ movl copy_and_run, %eax
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr