diff options
Diffstat (limited to 'src/cpu/amd')
| -rw-r--r-- | src/cpu/amd/model_10xxx/defaults.h | 9 | ||||
| -rw-r--r-- | src/cpu/amd/model_10xxx/fidvid.c | 36 |
2 files changed, 33 insertions, 12 deletions
diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h index 9a0e349e0a..b00ae487cc 100644 --- a/src/cpu/amd/model_10xxx/defaults.h +++ b/src/cpu/amd/model_10xxx/defaults.h @@ -68,7 +68,7 @@ static const struct { 1 << 24, 0x00000000, 1 << 24, 0x00000000 }, /* Erratum #261 [DIS_PIGGY_BACK_SCRUB]=1 */ - { LS_CFG, AMD_FAM10_GT_B0, AMD_PTYPE_ALL, + { LS_CFG, AMD_DR_GT_B0, AMD_PTYPE_ALL, 0 << 1, 0x00000000, 1 << 1, 0x00000000 }, /* IDX_MATCH_ALL=0 */ @@ -261,8 +261,11 @@ static const struct { { 3, 0xA0, AMD_FAM10_ALL, AMD_PTYPE_MOB | AMD_PTYPE_DSK, 0x00000080, 0x00000080 }, /* [7] PSIVidEnable */ - { 3, 0xA0, AMD_FAM10_ALL, AMD_PTYPE_ALL, - 0x00001800, 0x000003800 }, /* [13:11] PllLockTime = 3 */ + { 3, 0xA0, AMD_DR_Bx, AMD_PTYPE_ALL, + 0x00002800, 0x000003800 }, /* [13:11] PllLockTime = 5 */ + + { 3, 0xA0, (AMD_FAM10_ALL & ~(AMD_DR_Bx)), AMD_PTYPE_ALL, + 0x00000800, 0x000003800 }, /* [13:11] PllLockTime = 1 */ /* Reported Temp Control Register */ { 3, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL, diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c index 4fec71542e..fc54d16e23 100644 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ b/src/cpu/amd/model_10xxx/fidvid.c @@ -275,19 +275,18 @@ static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) { } -static void config_power_ctrl_misc_reg(device_t dev) { +static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) { /* check PVI/SVI */ u32 dword = pci_read_config32(dev, 0xA0); + + /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xA0[VSSlamVidMod] */ + /* PllLockTime and PsiVidEn set in ruleset in defaults.h */ if (dword & PVI_MODE) { /* PVI */ /* set slamVidMode to 0 for PVI */ - dword &= VID_SLAM_OFF | PLLLOCK_OFF; - dword |= PLLLOCK_DFT_L; - pci_write_config32(dev, 0xA0, dword); + dword &= VID_SLAM_OFF ; } else { /* SVI */ /* set slamVidMode to 1 for SVI */ - dword &= PLLLOCK_OFF; - dword |= PLLLOCK_DFT_L | VID_SLAM_ON; - pci_write_config32(dev, 0xA0, dword); + dword |= VID_SLAM_ON; u32 dtemp = dword; @@ -299,7 +298,27 @@ static void config_power_ctrl_misc_reg(device_t dev) { else dword &= PWR_PLN_OFF; pci_write_config32(dev, 0xD8, dword); + + dword = dtemp; + } + /* set the rest of A0 since we're at it... */ + + if (cpuRev & (AMD_DA_Cx | AMD_RB_C3 )) { + dword |= NB_PSTATE_FORCE_ON; + } // else should we clear it ? + + + if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32) ) { + dword |= BP_INS_TRI_EN_ON ; } + + /* TODO: look into C1E state and F3xA0[IdleExitEn]*/ + #if CONFIG_SVI_HIGH_FREQ + if (cpuRev & AMD_FAM10_C3) { + dword |= SVI_HIGH_FREQ_ON; + } + #endif + pci_write_config32(dev, 0xA0, dword); } static void config_nb_syn_ptr_adj(device_t dev) { @@ -344,8 +363,7 @@ static void prep_fid_change(void) config_clk_power_ctrl_reg0(i,cpuRev,procPkg); - config_power_ctrl_misc_reg(dev); - + config_power_ctrl_misc_reg(dev,cpuRev,procPkg); config_nb_syn_ptr_adj(dev); config_acpi_pwr_state_ctrl_regs(dev); |