diff options
Diffstat (limited to 'src/cpu/amd/pi/00730F01')
| -rw-r--r-- | src/cpu/amd/pi/00730F01/fixme.c | 8 | ||||
| -rw-r--r-- | src/cpu/amd/pi/00730F01/update_microcode.c | 66 |
2 files changed, 36 insertions, 38 deletions
diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index 689fdecd15..1e6cb3d30d 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -11,10 +11,10 @@ void amd_initcpuio(void) { - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; /* Enable legacy video routing: D18F1xF4 VGA Enable */ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); diff --git a/src/cpu/amd/pi/00730F01/update_microcode.c b/src/cpu/amd/pi/00730F01/update_microcode.c index 60484dee7a..7c15f9b12c 100644 --- a/src/cpu/amd/pi/00730F01/update_microcode.c +++ b/src/cpu/amd/pi/00730F01/update_microcode.c @@ -18,33 +18,33 @@ #define F16H_MPB_MAX_SIZE 3458 #define F16H_MPB_DATA_OFFSET 32 - /* - * STRUCTURE OF A MICROCODE (UCODE) FILE FOR FAM16h - * Microcode Patch Block - * Microcode Header - * Microcode "Blob" - * ... - * ... - * (end of file) - * - * - * MICROCODE HEADER (offset 0 bytes from start of file) - * Total size = 32 bytes - * [0:3] Date code (32 bits) - * [4:7] Patch level (32 bits) - * [8:9] Microcode patch data ID (16 bits) - * [10:15] Reserved (48 bits) - * [16:19] Chipset 1 device ID (32 bits) - * [20:23] Chipset 2 device ID (32 bits) - * [24:25] Processor Revisions ID (16 bits) - * [26] Chipset 1 revision ID (8 bits) - * [27] Chipset 2 revision ID (8 bits) - * [28:31] Reserved (32 bits) - * - * MICROCODE BLOB (offset += 32) - * Total size = m bytes - * - */ +/* + * STRUCTURE OF A MICROCODE (UCODE) FILE FOR FAM16h + * Microcode Patch Block + * Microcode Header + * Microcode "Blob" + * ... + * ... + * (end of file) + * + * + * MICROCODE HEADER (offset 0 bytes from start of file) + * Total size = 32 bytes + * [0:3] Date code (32 bits) + * [4:7] Patch level (32 bits) + * [8:9] Microcode patch data ID (16 bits) + * [10:15] Reserved (48 bits) + * [16:19] Chipset 1 device ID (32 bits) + * [20:23] Chipset 2 device ID (32 bits) + * [24:25] Processor Revisions ID (16 bits) + * [26] Chipset 1 revision ID (8 bits) + * [27] Chipset 2 revision ID (8 bits) + * [28:31] Reserved (32 bits) + * + * MICROCODE BLOB (offset += 32) + * Total size = m bytes + * + */ struct microcode { uint32_t date_code; @@ -76,18 +76,17 @@ static void apply_microcode_patch(const struct microcode *m) wrmsr(MSR_PATCH_LOADER, msr); - printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n", - m->patch_id); + printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n", m->patch_id); msr = rdmsr(IA32_BIOS_SIGN_ID); new_patch_id = msr.lo; if (new_patch_id == m->patch_id) printk(BIOS_INFO, "microcode: being updated to patch id = 0x%08x succeeded\n", - new_patch_id); + new_patch_id); else printk(BIOS_ERR, "microcode: being updated to patch id = 0x%08x failed\n", - new_patch_id); + new_patch_id); } static uint16_t get_equivalent_processor_rev_id(void) @@ -98,7 +97,7 @@ static uint16_t get_equivalent_processor_rev_id(void) } static void amd_update_microcode(const void *ucode, size_t ucode_len, - uint16_t equivalent_processor_rev_id) + uint16_t equivalent_processor_rev_id) { const struct microcode *m; const uint8_t *c = ucode; @@ -122,8 +121,7 @@ void amd_update_microcode_from_cbfs(void) return; } - if (ucode_len > F16H_MPB_MAX_SIZE || - ucode_len < F16H_MPB_DATA_OFFSET) { + if (ucode_len > F16H_MPB_MAX_SIZE || ucode_len < F16H_MPB_DATA_OFFSET) { printk(BIOS_DEBUG, "microcode file invalid. Skipping updates.\n"); return; } |