6 files changed, 0 insertions, 256 deletions
diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig
deleted file mode 100644
index 1cdfb1d7be..0000000000
--- a/src/cpu/amd/pi/00660F01/Kconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-config CPU_AMD_PI_00660F01
-	bool
-	select X86_AMD_FIXED_MTRRS
-
-if CPU_AMD_PI_00660F01
-
-config CPU_ADDR_BITS
-	int
-	default 48
-
-endif
diff --git a/src/cpu/amd/pi/00660F01/Makefile.inc b/src/cpu/amd/pi/00660F01/Makefile.inc
deleted file mode 100644
index 69635fc1f2..0000000000
--- a/src/cpu/amd/pi/00660F01/Makefile.inc
+++ /dev/null
@@ -1,14 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-romstage-y += fixme.c
-ramstage-y += fixme.c
-ramstage-y += chip_name.c
-ramstage-y += model_15_init.c
-
-subdirs-y += ../../mtrr
-subdirs-y += ../../../x86/tsc
-subdirs-y += ../../../x86/lapic
-subdirs-y += ../../../x86/cache
-subdirs-y += ../../../x86/mtrr
-subdirs-y += ../../../x86/pae
-subdirs-y += ../../../x86/smm
diff --git a/src/cpu/amd/pi/00660F01/acpi/cpu.asl b/src/cpu/amd/pi/00660F01/acpi/cpu.asl
deleted file mode 100644
index ede5021e03..0000000000
--- a/src/cpu/amd/pi/00660F01/acpi/cpu.asl
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * Processor Object
- *
- */
-Scope (\_SB) {	/* define processor scope */
-
-	Device (P000) {
-	Name(_HID, "ACPI0007")
-	Name(_UID, 0)
-	}
-
-	Device (P001) {
-	Name(_HID, "ACPI0007")
-	Name(_UID, 1)
-	}
-
-	Device (P002) {
-	Name(_HID, "ACPI0007")
-	Name(_UID, 2)
-	}
-
-	Device (P003) {
-	Name(_HID, "ACPI0007")
-	Name(_UID, 3)
-	}
-
-	Device (P004) {
-	Name(_HID, "ACPI0007")
-	Name(_UID, 4)
-	}
-
-	Device (P005) {
-	Name(_HID, "ACPI0007")
-	Name(_UID, 5)
-	}
-
-	Device (P006) {
-	Name(_HID, "ACPI0007")
-	Name(_UID, 6)
-	}
-
-	Device (P007) {
-	Name(_HID, "ACPI0007")
-	Name(_UID, 7)
-	}
-} /* End _SB scope */
diff --git a/src/cpu/amd/pi/00660F01/chip_name.c b/src/cpu/amd/pi/00660F01/chip_name.c
deleted file mode 100644
index 06fa4442ec..0000000000
--- a/src/cpu/amd/pi/00660F01/chip_name.c
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-
-struct chip_operations cpu_amd_pi_00660F01_ops = {
-	CHIP_NAME("AMD CPU Family 15h Model 60h-6Fh")
-};
diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c
deleted file mode 100644
index 9b208ecc4c..0000000000
--- a/src/cpu/amd/pi/00660F01/fixme.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-#include <Porting.h>
-#include <AGESA.h>
-#include <amdlib.h>
-
-void amd_initcpuio(void)
-{
-	UINT64                        MsrReg;
-	UINT32                        PciData;
-	PCI_ADDR                      PciAddress;
-	AMD_CONFIG_PARAMS             StdHeader;
-
-	/* Enable legacy video routing: D18F1xF4 VGA Enable */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
-	PciData = 1;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-	/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
-	 * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
-	 * set to non-posted regions.
-	 */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
-	/* last address before processor local APIC at FEE00000 */
-	PciData = 0x00FEDF00;
-	/* set NP (non-posted) bit */
-	PciData |= 1 << 7;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
-	/* lowest NP address is HPET at FED00000 */
-	PciData = (0xFED00000 >> 8) | 3;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-	/* Map the remaining PCI hole as posted MMIO */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
-	PciData = 0x00FECF00; /* last address before non-posted range */
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
-	MsrReg = (MsrReg >> 8) | 3;
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
-	PciData = (UINT32)MsrReg;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-	/* Send all IO (0000-FFFF) to southbridge. */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
-	PciData = 0x0000F000;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
-	PciData = 0x00000003;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-}
diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c
deleted file mode 100644
index 4bb289622c..0000000000
--- a/src/cpu/amd/pi/00660F01/model_15_init.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/msr.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <cpu/x86/pae.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/cache.h>
-
-#include <amdlib.h>
-#include <PspBaseLib.h>
-
-void PSPProgBar3Msr(void *Buffer);
-
-void PSPProgBar3Msr(void *Buffer)
-{
-	u32 Bar3Addr;
-	u64 Tmp64;
-	/* Get Bar3 Addr */
-	Bar3Addr = PspLibPciReadPspConfig(0x20);
-	Tmp64 = Bar3Addr;
-	printk(BIOS_DEBUG, "Bar3=%llx\n", Tmp64);
-	LibAmdMsrWrite(0xC00110A2, &Tmp64, NULL);
-	LibAmdMsrRead(0xC00110A2, &Tmp64, NULL);
-}
-
-static void model_15_init(struct device *dev)
-{
-	printk(BIOS_DEBUG, "Model 15 Init.\n");
-
-	u8 i;
-	msr_t msr;
-	int num_banks;
-	int msrno;
-#if CONFIG(LOGICAL_CPUS)
-	u32 siblings;
-#endif
-
-	disable_cache();
-	/* Enable access to AMD RdDram and WrDram extension bits */
-	msr = rdmsr(SYSCFG_MSR);
-	msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
-	msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
-	wrmsr(SYSCFG_MSR, msr);
-
-	// BSP: make a0000-bffff UC, c0000-fffff WB
-	msr.lo = msr.hi = 0;
-	wrmsr(MTRR_FIX_16K_A0000, msr);
-	msr.lo = msr.hi = 0x1e1e1e1e;
-	wrmsr(MTRR_FIX_64K_00000, msr);
-	wrmsr(MTRR_FIX_16K_80000, msr);
-	for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++)
-		wrmsr(msrno, msr);
-
-	msr = rdmsr(SYSCFG_MSR);
-	msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
-	msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
-	wrmsr(SYSCFG_MSR, msr);
-
-	x86_mtrr_check();
-	x86_enable_cache();
-
-	/* zero the machine check error status registers */
-	msr = rdmsr(IA32_MCG_CAP);
-	num_banks = msr.lo & MCA_BANKS_MASK;
-	msr.lo = 0;
-	msr.hi = 0;
-	for (i = 0; i < num_banks; i++)
-		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
-
-	/* Enable the local CPU APICs */
-	setup_lapic();
-
-#if CONFIG(LOGICAL_CPUS)
-	siblings = cpuid_ecx(0x80000008) & 0xff;
-
-	if (siblings > 0) {
-		msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
-		msr.lo |= 1 << 28;
-		wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
-
-		msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
-		msr.hi |= 1 << (33 - 32);
-		wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
-	}
-	printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
-#endif
-	PSPProgBar3Msr(NULL);
-
-	/* DisableCf8ExtCfg */
-	msr = rdmsr(NB_CFG_MSR);
-	msr.hi &= ~(1 << (46 - 32));
-	wrmsr(NB_CFG_MSR, msr);
-
-	/* Write protect SMM space with SMMLOCK. */
-	msr = rdmsr(HWCR_MSR);
-	msr.lo |= (1 << 0);
-	wrmsr(HWCR_MSR, msr);
-}
-
-static struct device_operations cpu_dev_ops = {
-	.init = model_15_init,
-};
-
-static const struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_AMD, 0x660f00 },
-	{ X86_VENDOR_AMD, 0x660f01 },
-	{ 0, 0 },
-};
-
-static const struct cpu_driver model_15 __cpu_driver = {
-	.ops      = &cpu_dev_ops,
-	.id_table = cpu_table,
-};