aboutsummaryrefslogtreecommitdiff
path: root/src/cpu/amd/model_lx/cpureginit.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu/amd/model_lx/cpureginit.c')
-rw-r--r--src/cpu/amd/model_lx/cpureginit.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/amd/model_lx/cpureginit.c b/src/cpu/amd/model_lx/cpureginit.c
index 492ee8fac0..62fa973a8c 100644
--- a/src/cpu/amd/model_lx/cpureginit.c
+++ b/src/cpu/amd/model_lx/cpureginit.c
@@ -248,8 +248,8 @@ void cpuRegInit(void)
msr.hi |= ARB_UPPER_QUACK_EN_SET;
wrmsr(msrnum, msr);
- /* GLIU port active enable, limit south pole masters
- * (AES and PCI) to one outstanding transaction.
+ /* GLIU port active enable, limit south pole masters
+ * (AES and PCI) to one outstanding transaction.
*/
print_debug(" GLIU port active enable\n");
msrnum = GLIU1_PORT_ACTIVE;