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-rw-r--r--src/cpu/amd/model_gx2/cpubug.c42
-rw-r--r--src/cpu/amd/model_gx2/cpureginit.c28
2 files changed, 35 insertions, 35 deletions
diff --git a/src/cpu/amd/model_gx2/cpubug.c b/src/cpu/amd/model_gx2/cpubug.c
index 82570f5b0a..f900661959 100644
--- a/src/cpu/amd/model_gx2/cpubug.c
+++ b/src/cpu/amd/model_gx2/cpubug.c
@@ -50,8 +50,8 @@ pcideadlock(void)
msr_t msr;
/*
- * forces serialization of all load misses. Setting this bit prevents the
- * DM pipe from backing up if a read request has to be held up waiting
+ * forces serialization of all load misses. Setting this bit prevents the
+ * DM pipe from backing up if a read request has to be held up waiting
* for PCI writes to complete.
*/
msr = rdmsr(CPU_DM_CONFIG0);
@@ -61,14 +61,14 @@ pcideadlock(void)
wrmsr(CPU_DM_CONFIG0, msr);
/* interlock instruction fetches to WS regions with data accesses.
- * This prevents an instruction fetch from going out to PCI if the
+ * This prevents an instruction fetch from going out to PCI if the
* data side is about to make a request.
*/
msr = rdmsr(CPU_IM_CONFIG);
msr.lo |= IM_CONFIG_LOWER_QWT_SET;
wrmsr(CPU_IM_CONFIG, msr);
-
- /* write serialize memory hole to PCI. Need to unWS when something is
+
+ /* write serialize memory hole to PCI. Need to unWS when something is
* shadowed regardless of cachablility.
*/
msr.lo = 0x021212121;
@@ -78,7 +78,7 @@ pcideadlock(void)
wrmsr( CPU_RCONF_E0_FF, msr);
}
-/****************************************************************************
+/****************************************************************************
*
* CPUbug784
*
@@ -176,7 +176,7 @@ eng2900(void)
wrmsr(0x3003, msr);
/* change this value to zero if you need to disable this BTB SWAPSiF. */
- if (1) {
+ if (1) {
/* Disable enable_actions in DIAGCTL while setting up GLCP */
msr.hi = 0;
@@ -192,16 +192,16 @@ eng2900(void)
msr.lo = 2;
wrmsr(MSR_GLCP + 0x0016, msr);
- /* The code below sets up the CPU to stall for 4 GeodeLink
- * clocks when CPU is snooped. Because setting XSTATE to 0
- * overrides any other XSTATE action, the code will always
- * stall for 4 GeodeLink clocks after a snoop request goes
- * away even if it occured a clock or two later than a
- * different snoop; the stall signal will never 'glitch high'
+ /* The code below sets up the CPU to stall for 4 GeodeLink
+ * clocks when CPU is snooped. Because setting XSTATE to 0
+ * overrides any other XSTATE action, the code will always
+ * stall for 4 GeodeLink clocks after a snoop request goes
+ * away even if it occured a clock or two later than a
+ * different snoop; the stall signal will never 'glitch high'
* for only one or two CPU clocks with this code.
*/
- /* Send mb0 port 3 requests to upper GeodeLink diag bits
+ /* Send mb0 port 3 requests to upper GeodeLink diag bits
[63:32] */
msr.hi = 0;
msr.lo = 0x80338041;
@@ -222,25 +222,25 @@ eng2900(void)
msr.lo = 0;
wrmsr(MSR_GLCP + 0x004D, msr);
- /* Writing action number 13: XSTATE=0 to occur when CPU is
+ /* Writing action number 13: XSTATE=0 to occur when CPU is
snooped unless we're stalled */
msr.hi = 0;
msr.lo = 0x00400000;
wrmsr(MSR_GLCP + 0x0075, msr);
- /* Writing action number 11: inc XSTATE every GeodeLink clock
+ /* Writing action number 11: inc XSTATE every GeodeLink clock
unless we're idle */
msr.hi = 0;
msr.lo = 0x30000;
wrmsr(MSR_GLCP + 0x0073, msr);
- /* Writing action number 5: STALL_CPU_PIPE when exitting idle
+ /* Writing action number 5: STALL_CPU_PIPE when exitting idle
state or not in idle state */
msr.hi = 0;
msr.lo = 0x00430000;
wrmsr(MSR_GLCP + 0x006D, msr);
- /* Writing DIAGCTL Register to enable the stall action and to
+ /* Writing DIAGCTL Register to enable the stall action and to
let set5m watch the upper GeodeLink diag bits. */
msr.hi = 0;
msr.lo = 0x80004000;
@@ -338,7 +338,7 @@ static void bug118339(void)
/***/
/****************************************************************************/
static void disablememoryreadorder(void)
-{
+{
msr_t msr;
msr = rdmsr(MC_CF8F_DATA);
@@ -365,7 +365,7 @@ cpubug(void)
case 0x20:
pcideadlock();
eng1398();
- /* cs 5530 bug; ignore
+ /* cs 5530 bug; ignore
bug752();
*/
break;
@@ -376,7 +376,7 @@ cpubug(void)
bug118339();
break;
case 0x22:
- case 0x30:
+ case 0x30:
break;
default:
printk(BIOS_ERR, "unknown rev %x, bailing\n", rev);
diff --git a/src/cpu/amd/model_gx2/cpureginit.c b/src/cpu/amd/model_gx2/cpureginit.c
index 5e786910c5..3cb3cf1a58 100644
--- a/src/cpu/amd/model_gx2/cpureginit.c
+++ b/src/cpu/amd/model_gx2/cpureginit.c
@@ -18,7 +18,7 @@ BIST(void){
msr = rdmsr(msrnum);
msr.lo |= DM_CONFIG0_LOWER_DCDIS_SET;
wrmsr(msrnum, msr);
-
+
msr.lo = 0x00000003F;
msr.hi = 0x000000000;
msrnum = CPU_DM_BIST;
@@ -29,7 +29,7 @@ BIST(void){
msr.lo &= 0x0F3FF0000;
if (msr.lo != 0xfeff0000)
goto BISTFail;
-
+
msrnum = CPU_DM_CONFIG0;
msr = rdmsr(msrnum);
msr.lo &= ~ DM_CONFIG0_LOWER_DCDIS_SET;
@@ -89,58 +89,58 @@ cpuRegInit (void){
msr.hi = 0;
msr.lo = DIAG_SEL1_SET | DIAG_SET0_SET;
wrmsr(msrnum, msr);
-
+
/* Set up GLCP to grab BTM data.*/
msrnum = 0x04C00000C; /* GLCP_DBGOUT MSR*/
msr.hi = 0x0;
msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out,*/
wrmsr(msrnum, msr); /* exchange it to anything else to prevent this*/
-
+
/* ;Turn off debug clock*/
msrnum = 0x04C000016; /* DBG_CLK_CTL*/
msr.lo = 0x00; /* No clock*/
msr.hi = 0x00;
wrmsr(msrnum, msr);
-
+
/* ;Set debug clock to CPU*/
msrnum = 0x04C000016; /* DBG_CLK_CTL*/
msr.lo = 0x01; /* CPU CLOCK*/
msr.hi = 0x00;
wrmsr(msrnum, msr);
-
+
/* ;Set fifo ctl to BTM bits wide*/
msrnum = 0x04C00005E; /* FIFO_CTL*/
msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit)*/
wrmsr(msrnum, msr); /* Bit [23:21] are position (100 = CPU downto0)*/
/* Bit [19] sets it up in slow data mode.*/
-
+
/* ;enable fifo loading - BTM sizing will constrain*/
/* ; only valid BTM packets to load - this action should always be on*/
-
+
msrnum = 0x04C00006F; /* GLCP ACTION7 - load fifo*/
msr.lo = 0x00000F000; /* Any nibble all 1's will always trigger*/
msr.hi = 0x000000000; /* */
wrmsr(msrnum, msr);
-
+
/* ;start storing diag data in the fifo*/
msrnum = 0x04C00005F; /* DIAG CTL*/
msr.lo = 0x080000000; /* enable actions*/
msr.hi = 0x000000000;
wrmsr(msrnum, msr);
-
+
/* Set up delay on data lines, so that the hold time*/
/* is 1 ns.*/
msrnum = 0x04C00000D ; /* GLCP IO DELAY CONTROLS*/
msr.lo = 0x082b5ad68;
msr.hi = 0x080ad6b57; /* RGB delay = 0x07*/
wrmsr(msrnum, msr);
-
+
/* Set up DF to output diag information on DF pins.*/
msrnum = DF_GLD_MSR_MASTER_CONF;
msr.lo = 0x0220;
msr.hi = 0;
wrmsr(msrnum, msr);
-
+
msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR*/
msr.hi = 0x0;
msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out,*/
@@ -237,7 +237,7 @@ cpuRegInit (void){
/* */
/* This code disables the data cache. Don't execute this
* unless you're testing something.
- */
+ */
/* Allow NVRam to override DM Setup*/
/*if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {*/
{
@@ -249,7 +249,7 @@ cpuRegInit (void){
}
/* This code disables the instruction cache. Don't execute
* this unless you're testing something.
- */
+ */
/* Allow NVRam to override IM Setup*/
/*if (getnvram( TOKEN_CACHE_IM_MODE) ==1) {*/
{
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 06:32:46 +0000