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Diffstat (limited to 'src/cpu/amd/family_10h-family_15h')
-rw-r--r--src/cpu/amd/family_10h-family_15h/Makefile.inc1
-rw-r--r--src/cpu/amd/family_10h-family_15h/init_cpus.c4
2 files changed, 3 insertions, 2 deletions
diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc
index c540320bfb..2ed76e1e1f 100644
--- a/src/cpu/amd/family_10h-family_15h/Makefile.inc
+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc
@@ -1,4 +1,5 @@
romstage-y += ../../x86/mtrr/earlymtrr.c
+romstage-y += ../car/post_cache_as_ram.c
romstage-y += init_cpus.c
diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
index f5a949cede..0ecd040253 100644
--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
+++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
@@ -34,7 +34,7 @@
#include <southbridge/amd/sb800/sb800.h>
#endif
-#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/car/disable_cache_as_ram.c"
#if IS_ENABLED(CONFIG_PCI_IO_CFG_EXT)
static void set_EnableCf8ExtCfg(void)
@@ -353,7 +353,7 @@ static void STOP_CAR_AND_CPU(uint8_t skip_sharedc_config, uint32_t apicid)
}
}
- disable_cache_as_ram(skip_sharedc_config); // inline
+ disable_cache_as_ram_real(skip_sharedc_config); // inline
/* Mark the core as sleeping */
lapic_write(LAPIC_MSG_REG, (apicid << 24) | F10_APSTATE_ASLEEP);