diff options
Diffstat (limited to 'src/cpu/amd/agesa')
-rw-r--r-- | src/cpu/amd/agesa/Kconfig | 5 | ||||
-rw-r--r-- | src/cpu/amd/agesa/Makefile.inc | 1 | ||||
-rw-r--r-- | src/cpu/amd/agesa/apic_timer.c | 59 |
3 files changed, 5 insertions, 60 deletions
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 39175fc79e..d57bded604 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -26,6 +26,7 @@ config CPU_AMD_AGESA default y if CPU_AMD_AGESA_FAMILY15_TN default n select TSC_SYNC_LFENCE + select UDELAY_LAPIC if CPU_AMD_AGESA @@ -44,6 +45,10 @@ config XIP_ROM_SIZE In order to execute romstage in place on the flash rom, more space is required to be set as write through caching. +config UDELAY_LAPIC_FIXED_FSB + int + default 200 + source src/cpu/amd/agesa/family10/Kconfig source src/cpu/amd/agesa/family12/Kconfig source src/cpu/amd/agesa/family14/Kconfig diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 6c6cb89eda..401be3e532 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -24,5 +24,4 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c -ramstage-y += apic_timer.c cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/apic_timer.c b/src/cpu/amd/agesa/apic_timer.c deleted file mode 100644 index ec6ddd5473..0000000000 --- a/src/cpu/amd/agesa/apic_timer.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#include <stdint.h> -#include <delay.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> - -/* NOTE: We use the APIC TIMER register is to hold flags for AP init during - * pre-memory init (__PRE_RAM__). Don't use init_timer() and udelay is - * redirected to udelay_tsc(). - */ - - -void init_timer(void) -{ - /* Set the apic timer to no interrupts and periodic mode */ - lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0)); - - /* Set the divider to 1, no divider */ - lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); - - /* Set the initial counter to 0xffffffff */ - lapic_write(LAPIC_TMICT, 0xffffffff); - -} - - -void udelay(u32 usecs) -{ - u32 start, value, ticks; - /* Calculate the number of ticks to run, our FSB runs a 200Mhz */ - ticks = usecs * 200; - start = lapic_read(LAPIC_TMCCT); - do { - value = lapic_read(LAPIC_TMCCT); - } while((start - value) < ticks); - -} |