6 files changed, 0 insertions, 231 deletions
diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig
deleted file mode 100644
index 60bf64f2db..0000000000
--- a/src/cpu/amd/agesa/family16kb/Kconfig
+++ /dev/null
@@ -1,21 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-config CPU_AMD_AGESA_FAMILY16_KB
-	bool
-	select SMM_ASEG
-	select X86_AMD_FIXED_MTRRS
-
-if CPU_AMD_AGESA_FAMILY16_KB
-
-config FORCE_AM1_SOCKET_SUPPORT
-	bool
-	default n
-	help
-		Force AGESA to ignore package type mismatch between CPU and northbridge
-		in memory code. This enables Socket AM1 support with current AGESA
-		version for Kabini platform.
-		Enable this option only if you have Socket AM1 board.
-		Note that the AGESA release shipped with coreboot does not officially
-		support the AM1 socket. Selecting this option might damage your hardware.
-
-endif
diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc
deleted file mode 100644
index 9464372d22..0000000000
--- a/src/cpu/amd/agesa/family16kb/Makefile.inc
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-romstage-y += fixme.c
-
-ramstage-y += fixme.c
-ramstage-y += chip_name.c
-ramstage-y += model_16_init.c
-
-subdirs-y += ../../mtrr
diff --git a/src/cpu/amd/agesa/family16kb/acpi/cpu.asl b/src/cpu/amd/agesa/family16kb/acpi/cpu.asl
deleted file mode 100644
index d589ae8c42..0000000000
--- a/src/cpu/amd/agesa/family16kb/acpi/cpu.asl
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * Processor Object
- *
- */
-Scope (\_SB) {/* define processor scope */
-	Device (P000) {
-	Name(_HID, "ACPI0007")
-	Name(_UID, 0)
-	}
-
-	Device (P001) {
-	Name(_HID, "ACPI0007")
-	Name(_UID, 1)
-	}
-
-	Device (P002) {
-	Name(_HID, "ACPI0007")
-	Name(_UID, 2)
-	}
-
-	Device (P003) {
-	Name(_HID, "ACPI0007")
-	Name(_UID, 3)
-	}
-
-	Device (P004) {
-	Name(_HID, "ACPI0007")
-	Name(_UID, 4)
-	}
-
-	Device (P005) {
-	Name(_HID, "ACPI0007")
-	Name(_UID, 5)
-	}
-
-	Device (P006) {
-	Name(_HID, "ACPI0007")
-	Name(_UID, 6)
-	}
-
-	Device (P007) {
-	Name(_HID, "ACPI0007")
-	Name(_UID, 7)
-	}
-} /* End _SB scope */
diff --git a/src/cpu/amd/agesa/family16kb/chip_name.c b/src/cpu/amd/agesa/family16kb/chip_name.c
deleted file mode 100644
index 0ca021cef4..0000000000
--- a/src/cpu/amd/agesa/family16kb/chip_name.c
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-
-struct chip_operations cpu_amd_agesa_family16kb_ops = {
-	CHIP_NAME("AMD CPU Family 16h Model 00h-0Fh")
-};
diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c
deleted file mode 100644
index da2744c154..0000000000
--- a/src/cpu/amd/agesa/family16kb/fixme.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/hpet.h>
-#include <cpu/amd/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-#include <AGESA.h>
-#include <amdlib.h>
-
-void amd_initcpuio(void)
-{
-	UINT64 MsrReg;
-	UINT32 PciData;
-	PCI_ADDR PciAddress;
-	AMD_CONFIG_PARAMS StdHeader;
-
-	/* Enable legacy video routing: D18F1xF4 VGA Enable */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
-	PciData = 1;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-	/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
-	 * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
-	 * set to non-posted regions.
-	 */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
-	PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
-	PciData |= 1 << 7;    /* set NP (non-posted) bit */
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
-	PciData = (HPET_BASE_ADDRESS >> 8) | 3; /* lowest NP address is HPET at FED00000 */
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-	/* Map the remaining PCI hole as posted MMIO */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
-	PciData = 0x00FECF00; /* last address before non-posted range */
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
-	MsrReg = (MsrReg >> 8) | 3;
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
-	PciData = (UINT32)MsrReg;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-	/* Send all IO (0000-FFFF) to southbridge. */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
-	PciData = 0x0000F000;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
-	PciData = 0x00000003;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-}
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
deleted file mode 100644
index 0f1113638c..0000000000
--- a/src/cpu/amd/agesa/family16kb/model_16_init.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi.h>
-#include <amdblocks/cpu.h>
-#include <amdblocks/smm.h>
-#include <console/console.h>
-#include <cpu/amd/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/mtrr.h>
-#include <device/device.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-
-static void model_16_init(struct device *dev)
-{
-	printk(BIOS_DEBUG, "Model 16 Init.\n");
-
-	msr_t msr;
-	int msrno;
-#if CONFIG(LOGICAL_CPUS)
-	u32 siblings;
-#endif
-
-	/*
-	 * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set
-	 * by coreboot.
-	 */
-	disable_cache();
-	/* Enable access to AMD RdDram and WrDram extension bits */
-	msr = rdmsr(SYSCFG_MSR);
-	msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
-	msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
-	wrmsr(SYSCFG_MSR, msr);
-
-	// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
-	msr.lo = msr.hi = 0;
-	wrmsr(MTRR_FIX_16K_A0000, msr);
-	msr.lo = msr.hi = 0x1e1e1e1e;
-	wrmsr(MTRR_FIX_64K_00000, msr);
-	wrmsr(MTRR_FIX_16K_80000, msr);
-	for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++)
-		wrmsr(msrno, msr);
-
-	msr = rdmsr(SYSCFG_MSR);
-	msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
-	msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
-	wrmsr(SYSCFG_MSR, msr);
-
-	if (acpi_is_wakeup_s3())
-		restore_mtrr();
-
-	x86_mtrr_check();
-	enable_cache();
-
-	/* zero the machine check error status registers */
-	mca_clear_status();
-
-#if CONFIG(LOGICAL_CPUS)
-	siblings = get_cpu_count() - 1; // minus BSP
-
-	if (siblings > 0) {
-		msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
-		msr.lo |= 1 << 28;
-		wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
-
-		msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
-		msr.hi |= 1 << (33 - 32);
-		wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
-	}
-	printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
-#endif
-
-	/* DisableCf8ExtCfg */
-	msr = rdmsr(NB_CFG_MSR);
-	msr.hi &= ~(1 << (46 - 32));
-	wrmsr(NB_CFG_MSR, msr);
-
-	/* Write protect SMM space with SMMLOCK. */
-	lock_smm();
-}
-
-static struct device_operations cpu_dev_ops = {
-	.init = model_16_init,
-};
-
-static const struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_AMD, 0x700f00 },	/* KB-A0 */
-	{ 0, 0 },
-};
-
-static const struct cpu_driver model_15 __cpu_driver = {
-	.ops      = &cpu_dev_ops,
-	.id_table = cpu_table,
-};