1 files changed, 19 insertions, 30 deletions

diff --git a/src/cpu/amd/agesa/family15/romstage.c b/src/cpu/amd/agesa/family15/romstage.c
index 02495b0dd7..1c2330839f 100644
--- a/src/cpu/amd/agesa/family15/romstage.c
+++ b/src/cpu/amd/agesa/family15/romstage.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2017 Kyösti Mälkki
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -15,17 +16,16 @@
 
 #include <lib.h>
 #include <reset.h>
-#include <stdint.h>
-#include <arch/io.h>
-#include <arch/cpu.h>
-#include <console/console.h>
 #include <arch/stages.h>
-#include "cpu/x86/bist.h"
-#include "cpu/x86/lapic.h"
+#include <cpu/amd/agesa/s3_resume.h>
+
+#include <console/console.h>
 #include <cpu/amd/car.h>
+
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 #include <northbridge/amd/agesa/state_machine.h>
+
 #include "northbridge/amd/agesa/family10/reset_test.h"
 #include <nb_cimx.h>
 #include <sb_cimx.h>
@@ -35,39 +35,26 @@ void asmlinkage early_all_cores(void)
 	amd_initmmio();
 }
 
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void platform_once(struct sysinfo *cb)
 {
-	struct sysinfo *cb = NULL;
-	u32 val;
+	/*
+	 * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
+	 * Disable all Pcie Bridges to work around It.
+	 */
+	sr56x0_rd890_disable_pcie_bridge();
 
-	post_code(0x31);
+	nb_Poweron_Init();
 
-	/* Halt if there was a built in self test failure */
-	post_code(0x33);
-	report_bist_failure(bist);
+	sb_Poweron_Init();
 
 	board_BeforeAgesa(cb);
-	console_init();
-
-	val = cpuid_eax(1);
-	printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
-	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
+}
 
+void agesa_main(struct sysinfo *cb)
+{
 	post_code(0x37);
 	agesawrapper_amdinitreset();
 
-	if (!cpu_init_detectedx && boot_cpu()) {
-		post_code(0x38);
-		/*
-		 * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
-		 * Disable all Pcie Bridges to work around It.
-		 */
-		sr56x0_rd890_disable_pcie_bridge();
-		post_code(0x39);
-		nb_Poweron_Init();
-		post_code(0x3A);
-		sb_Poweron_Init();
-	}
 	post_code(0x3B);
 	agesawrapper_amdinitearly();
 
@@ -97,4 +84,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x51);
 	copy_and_run();
+
+	/* Not reached */
 }