diff options
Diffstat (limited to 'src/commonlib')
| -rw-r--r-- | src/commonlib/include/commonlib/coreboot_tables.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 6b5eb59cf8..76dce0a41b 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -95,6 +95,9 @@ enum { LB_TAG_OPTION_CHECKSUM = 0x00cc, }; +/* All table entry base addresses and sizes must be 4-byte aligned. */ +#define LB_ENTRY_ALIGN 4 + /* Since coreboot is usually compiled 32bit, gcc will align 64bit * types to 32bit boundaries. If the coreboot table is dumped on a * 64bit system, a uint64_t would be aligned to 64bit boundaries, @@ -104,7 +107,7 @@ enum { * to ensure compatibility. */ -typedef __aligned(4) uint64_t lb_uint64_t; +typedef __aligned(LB_ENTRY_ALIGN) uint64_t lb_uint64_t; struct lb_header { uint8_t signature[4]; /* LBIO */ @@ -203,6 +206,7 @@ struct lb_console { uint32_t tag; uint32_t size; uint16_t type; + uint8_t pad[2]; }; #define LB_TAG_CONSOLE_SERIAL8250 0 @@ -288,6 +292,7 @@ struct lb_framebuffer { uint8_t reserved_mask_pos; uint8_t reserved_mask_size; uint8_t orientation; + uint8_t pad[2]; }; struct lb_gpio { @@ -553,6 +558,7 @@ struct lb_tpm_physical_presence { uint32_t ppi_address; /* Address of ACPI PPI communication buffer */ uint8_t tpm_version; /* 1: TPM1.2, 2: TPM2.0 */ uint8_t ppi_version; /* BCD encoded */ + uint8_t pad[2]; }; |