3 files changed, 17 insertions, 3 deletions
diff --git a/src/arch/ppc64/include/arch/io.h b/src/arch/ppc64/include/arch/io.h
index 6dc0a84b6c..cfaae33f60 100644
--- a/src/arch/ppc64/include/arch/io.h
+++ b/src/arch/ppc64/include/arch/io.h
@@ -8,7 +8,9 @@
 /* Set MSB to 1 to ignore HRMOR */
 #define MMIO_GROUP0_CHIP0_LPC_BASE_ADDR 0x8006030000000000
 #define LPCHC_IO_SPACE 0xD0010000
+#define FLASH_IO_SPACE 0xFC000000
 #define LPC_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + LPCHC_IO_SPACE)
+#define FLASH_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + FLASH_IO_SPACE)
 #define MMIO_GROUP0_CHIP0_SCOM_BASE_ADDR 0x800603FC00000000
 
 /* Enforce In-order Execution of I/O */
diff --git a/src/arch/ppc64/rom_media.c b/src/arch/ppc64/rom_media.c
index 7d849e4cdb..2fd47669a8 100644
--- a/src/arch/ppc64/rom_media.c
+++ b/src/arch/ppc64/rom_media.c
@@ -1,11 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <arch/io.h>
 #include <boot_device.h>
 
-/* This assumes that the CBFS resides at 0x0, which is true for the default
- * configuration. */
 static const struct mem_region_device boot_dev =
-	MEM_REGION_DEV_RO_INIT(NULL, CONFIG_ROM_SIZE);
+	MEM_REGION_DEV_RO_INIT(FLASH_BASE_ADDR, CONFIG_ROM_SIZE);
 
 const struct region_device *boot_device_ro(void)
 {
diff --git a/src/arch/ppc64/stages.c b/src/arch/ppc64/stages.c
index 20ed723bf5..01b9efaba8 100644
--- a/src/arch/ppc64/stages.c
+++ b/src/arch/ppc64/stages.c
@@ -13,10 +13,23 @@
 
 #include <cbmem.h>
 #include <arch/stages.h>
+#include <cpu/power/spr.h>
 
 void stage_entry(uintptr_t stage_arg)
 {
+#if ENV_RAMSTAGE
+	uint64_t hrmor;
+#endif
+
 	if (!ENV_ROMSTAGE_OR_BEFORE)
 		_cbmem_top_ptr = stage_arg;
+
+#if ENV_RAMSTAGE
+	hrmor = read_spr(SPR_HRMOR);
+	asm volatile("sync; isync" ::: "memory");
+	write_spr(SPR_HRMOR, 0);
+	asm volatile("or 1,1,%0; slbia 7; sync; isync" :: "r"(hrmor) : "memory");
+#endif
+
 	main();
 }