4 files changed, 0 insertions, 297 deletions
diff --git a/src/arch/ppc/init/Config.lb b/src/arch/ppc/init/Config.lb
deleted file mode 100644
index 5fcae5f3c2..0000000000
--- a/src/arch/ppc/init/Config.lb
+++ /dev/null
@@ -1,2 +0,0 @@
-init crt0.S.lb
-initobject ppc_main.o
diff --git a/src/arch/ppc/init/crt0.S.lb b/src/arch/ppc/init/crt0.S.lb
deleted file mode 100644
index bbccc59213..0000000000
--- a/src/arch/ppc/init/crt0.S.lb
+++ /dev/null
@@ -1,137 +0,0 @@
-/* Copyright 2000  AG Electronics Ltd. */
-/* This code is distributed without warranty under the GPL v2 (see COPYING) */
-
-#define ASM
-#include "ppcreg.h"
-#include <ppc_asm.tmpl>
-
-.section ".rom.reset", "ax", @progbits
-
-.globl _start
-_start:
-	b	system_reset
-
-.section ".rom.exception_vectors", "ax", @progbits
-
-%%EXCEPTION_VECTOR_TABLE%%
-
-.section ".rom.data", "a", @progbits
-.section ".rom.text", "ax", @progbits
-
-system_reset:
-
-	/*
-	 * Do processor family initialization
-	 */
-%%FAMILY_INIT%%
-
-	/*
-	 * Do processor specific initialization
-	 */
-%%PROCESSOR_INIT%%
-
-#if CONFIG_USE_DCACHE_RAM == 1
-#define DCACHE_RAM_END	(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 1)
-	/*
-	 * Initialize data cache blocks 
-	 * (assumes cache block size of 32 bytes)
-	 *
-	 * NOTE: This may need to be moved to FAMILY_INIT if
-	 *       dcbz is not supported on all CPU's
-	 */
-	lis     r1, CONFIG_DCACHE_RAM_BASE@h
-	ori     r1, r1, CONFIG_DCACHE_RAM_BASE@l
-	li      r3, (CONFIG_DCACHE_RAM_SIZE / 32)
-	mtctr   r3
-0:      dcbz    r0, r1
-	addi    r1, r1, 32
-	bdnz    0b
-
-	/*
-	 * Set up stack in cache. The SP must be 16-byte (4-word) aligned
-	 * for SYSV EABI or 8-byte (2-word) aligned for PPC EABI, so we make 
-	 * it 16-byte aligned to cover both cases. Also we have to ensure that
-	 * the first word is located within the cache.
-	 */
-	lis     r1, (CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE)@h
-	ori     r1, r1, (CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE)@l
-	lis	r0, 0
-	stwu	r0, -4(r1)
-	stwu	r0, -4(r1)
-	stwu	r0, -4(r1)
-	stwu	r0, -4(r1)
-
-#if 0
-	/*
-	 * Clear stack
-	 */
-	lis	r4, CONFIG_DCACHE_RAM_BASE@h
-	ori	r4, r4, CONFIG_DCACHE_RAM_BASE@l
-	lis	r7, DCACHE_RAM_END@h
-	ori	r7, r7, DCACHE_RAM_END@l
-	lis	r5, 0
-1:	stwx	r5, 0, r4
-	addi	r4, r4, 4
-	cmp	0, 0, r4, r7
-	ble	1b
-	sync
-#endif
-
-	/*
-	 * Set up the EABI pointers, before we enter any C code
-	 */
-	lis     r13, _SDA_BASE_@h
-	ori     r13, r13, _SDA_BASE_@l
-	lis     r2, _SDA2_BASE_@h
-	ori     r2, r2, _SDA2_BASE_@l
-
-	/*
-	 * load start address into SRR0 for rfi
-	 */
-	lis	r3, ppc_main@h
-	ori 	r3, r3, ppc_main@l
-	mtspr	SRR0, r3
-
-	/*
-	 * load the current MSR into SRR1 so that it will be copied 
-	 * back into MSR on rfi
-	 */
-	mfmsr	r4
-	mtspr	SRR1, r4	// load SRR1 with r4
-
-	/*
-	 * If something returns after rfi then die
-	 */
-	lis	r3, dead@h
-	ori	r3, r3, dead@l
-	mtlr	r3
-
-	/*
-	 * Complete rest of initialization in C (ppc_main)
-	 */
-	rfi
-#endif /* CONFIG_USE_DCACHE_RAM */
-
-	/*
-	 * Stop here if something goes wrong
-	 */
-dead:
-	b	dead
-	/*NOTREACHED*/
-
-/* Remove need for ecrti.o and ectrn.o */
-.globl __init
-__init:
-.globl __fini
-__fini:
-.globl __CTOR_LIST__
-__CTOR_LIST__:
-.globl __CTOR_END__
-__CTOR_END__:
-.globl __DTOR_LIST__
-__DTOR_LIST__:
-.globl __DTOR_END__
-__DTOR_END__:
-        blr
-
-%%NORTHBRIDGE_INIT%%
diff --git a/src/arch/ppc/init/ldscript.lb b/src/arch/ppc/init/ldscript.lb
deleted file mode 100644
index 453c99c13b..0000000000
--- a/src/arch/ppc/init/ldscript.lb
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- *	Memory map:
- *
- *	CONFIG_ROMBASE		: start of ROM
- *	CONFIG_RESET			: reset vector (may be at top of ROM)
- *	_EXCEPTIONS_VECTORS	: exception table
- *
- *	CONFIG_ROMSTART 		: coreboot text 
- *				: payload text
- *
- *	CONFIG_RAMBASE		: address to copy payload
- */
-
-/*
- *	Written by Johan Rydberg, based on work by Daniel Kahlin.
- *      Rewritten by Eric Biederman
- *	Re-rewritten by Greg Watson for PPC
- */
-
-/*
- *	We use ELF as output format. So that we can
- *	debug the code in some form. 
- */
-
-OUTPUT_FORMAT("elf32-powerpc")
-ENTRY(_start)
-
-TARGET(binary)
-INPUT(coreboot_ram.rom)
-SECTIONS
-{
-	/* 
-	 * Absolute location of base of ROM 
-	 */
-	. = CONFIG_ROMBASE;
-
-	/*
-	 * Absolute location of reset vector. This may actually be at the
-	 * the top of ROM.
-	 */
-	. = CONFIG_RESET;
-	.reset . : {
-		*(.rom.reset);
-		. = ALIGN(16);
-	}
-
-	/*
-	 * Absolute location of exception vector table.
-	 */
-	. = CONFIG_EXCEPTION_VECTORS;
-	.exception_vectors . : {
-		*(.rom.exception_vectors);
-		. = ALIGN(16);
-	}
-
-	/*
-	 * Absolute location of coreboot initialization code in ROM.
-	 */
-	. = CONFIG_ROMSTART;
-	.rom . : {
-		_rom = .;
-		*(.rom.text);
-		*(.text);
-		*(.rom.data);
-		*(.rodata);
-		*(EXCLUDE_FILE(coreboot_ram.rom) .data);
-		. = ALIGN(16);
-		_erom = .;
-	}
-	_lrom = LOADADDR(.rom);
-	_elrom = LOADADDR(.rom) + SIZEOF(.rom);
-	
-	/*
-	 * Ram is the coreboot code that runs from RAM.
-	 */
-	.ram . : {
-		_ram = . ;
-		coreboot_ram.rom(*)
-		_eram = . ;
-	}
-
-	.sdata : {
-		_SDA_BASE_ = .;
-		*(.sdata)
-	}
-
-	.sdata2 : {
-		_SDA2_BASE_ = .;
-		*(.sdata2)
-	}
-
-
-
-	/*
-	 * Absolute location of where coreboot will be relocated in RAM.
-	 */
-	_iseg = CONFIG_RAMBASE;
-	_eiseg = _iseg + SIZEOF(.ram);
-	_liseg = _ram;
-	_eliseg = _eram;
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-	}
-}
diff --git a/src/arch/ppc/init/ppc_main.c b/src/arch/ppc/init/ppc_main.c
deleted file mode 100644
index 150deeea67..0000000000
--- a/src/arch/ppc/init/ppc_main.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* 
- * Copyright (C) 2003 by Greg Watson, Los Alamos National Laboratory
- * gwatson@lanl.gov
- */
-
-#include <board.h>
-#include <sdram.h>
-#include <cbfs.h>
-
-/*
- * At this point we're running out of flash with our
- * stack in cache ram. We need to do the following:
- *
- * - turn on real memory
- * - relocate our payload into real memory
- * - start hardwaremain() which does remainder of setup
- */
-
-extern void flush_dcache(void);
-
-void ppc_main(void)
-{
-	void (*payload)(void);
-
-	/*
- 	 * very early board initialization
-	 */
-	board_init();
-
-	/*
-	 * turn on memory
-	 */
-	memory_init();
-
-	/*
-	 * final initialization before jumping to payload
-	 */
-	board_init2();
-
-	/*
-	 * Flush cache now that memory is enabled.
-	 */
-	flush_dcache();
-
-	/*
-	 * Relocate payload (text & data)
-	 */
-	payload = cbfs_load_stage("fallback/coreboot_ram");
-	payload();
-
-	/* NOT REACHED */
-}