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Diffstat (limited to 'src/arch/arm64/armv8/cache.c')
-rw-r--r--src/arch/arm64/armv8/cache.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c
index d568f261ed..db9b3882bc 100644
--- a/src/arch/arm64/armv8/cache.c
+++ b/src/arch/arm64/armv8/cache.c
@@ -34,6 +34,7 @@
#include <stdint.h>
#include <arch/cache.h>
+#include <arch/cache_helpers.h>
#include <arch/lib_helpers.h>
void tlb_invalidate_all(void)
@@ -126,7 +127,7 @@ void dcache_mmu_disable(void)
{
uint32_t sctlr;
- flush_dcache_all();
+ flush_dcache_all(DCCISW);
sctlr = raw_read_sctlr_current();
sctlr &= ~(SCTLR_C | SCTLR_M);
raw_write_sctlr_current(sctlr);
@@ -143,6 +144,6 @@ void dcache_mmu_enable(void)
void cache_sync_instructions(void)
{
- flush_dcache_all(); /* includes trailing DSB (in assembly) */
+ flush_dcache_all(DCCISW); /* includes trailing DSB (in assembly) */
icache_invalidate_all(); /* includdes leading DSB and trailing ISB. */
}