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-rw-r--r--payloads/libpayload/include/coreboot_tables.h12
-rw-r--r--payloads/libpayload/include/sysinfo.h5
2 files changed, 17 insertions, 0 deletions
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 38bda55d75..02c9449b08 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -217,6 +217,18 @@ struct cb_vboot_handoff {
uint32_t vboot_handoff_size;
};
+#define CB_TAG_X86_ROM_MTRR 0x0021
+struct cb_x86_rom_mtrr {
+ uint32_t tag;
+ uint32_t size;
+ /* The variable range MTRR index covering the ROM. If one wants to
+ * enable caching the ROM, the variable MTRR needs to be set to
+ * write-protect. To disable the caching after enabling set the
+ * type to uncacheable. */
+ uint32_t index;
+};
+
+
#define CB_TAG_CMOS_OPTION_TABLE 0x00c8
struct cb_cmos_option_table {
u32 tag;
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index e05ef9f4d6..fd60dc34d9 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -99,6 +99,11 @@ struct sysinfo_t {
void *vdat_addr;
u32 vdat_size;
#endif
+
+#ifdef CONFIG_ARCH_X86
+ int x86_rom_var_mtrr_index;
+#endif
+
void *tstamp_table;
void *cbmem_cons;
void *mrc_cache;