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Diffstat (limited to 'Documentation/northbridge/intel/sandybridge/nri.md')
| -rw-r--r-- | Documentation/northbridge/intel/sandybridge/nri.md | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/northbridge/intel/sandybridge/nri.md b/Documentation/northbridge/intel/sandybridge/nri.md index 812cd23fdb..bf0b89f6a0 100644 --- a/Documentation/northbridge/intel/sandybridge/nri.md +++ b/Documentation/northbridge/intel/sandybridge/nri.md @@ -40,7 +40,7 @@ The memory initialization code has to take care of lots of duties: +---------+-------------------------------------------------------------------+------------+--------------+ ``` -## (Inoffical) register documentation +## (Unoffical) register documentation - [Sandy Bridge - Register documentation](nri_registers.md) ## Frequency selection @@ -83,7 +83,7 @@ in each DIMM's SPD. > **Note:** This feature is available since coreboot 4.4 ### MRC cache -The name *MRC cache* might be missleading as in case of *Native ram init* +The name *MRC cache* might be misleading as in case of *Native RAM init* there's no MRC, but for historical reasons it's still named *MRC cache*. The MRC cache is part of flash memory that is writeable by coreboot. At the end of the boot process coreboot will write the RAM training results to |