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Diffstat (limited to 'Documentation/mainboard/ocp')
| -rw-r--r-- | Documentation/mainboard/ocp/deltalake.md | 79 |
1 files changed, 49 insertions, 30 deletions
diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md index 57e727f9bd..9ef2357c0f 100644 --- a/Documentation/mainboard/ocp/deltalake.md +++ b/Documentation/mainboard/ocp/deltalake.md @@ -9,23 +9,25 @@ build/test/release cycle. OCP Delta Lake server platform is a component of multi-host server system Yosemite-V3. Both were announced by Facebook and Intel in [OCP virtual summit 2020]. -Delta Lake server is a single socket Cooper Lake Scalable Processor server. +Delta Lake server is a single socket Cooper Lake Scalable Processor (CPX-SP) server. Yosemite-V3 has multiple configurations. Depending on configurations, it may host up to 4 Delta Lake servers in one sled. -The Yosemite-V3 program has reached DVT exit. Facebook, Intel and partners +The Yosemite-V3 program is in PVT phase. Facebook, Intel and partners jointly develop FSP/coreboot/LinuxBoot stack on Delta Lake as an alternative -solution. This development is moving toward EVT exit equivalent status. +solution. This development reached EVT exit equivalent status. ## Required blobs This board currently requires: - FSP blob: The blob (Intel Cooper Lake Scalable Processor Firmware Support Package) is not yet available to the public. It will be made public some time after the MP - (Mass Production) of CooperLake Scalable Processor when the FSP is mature. + (Mass Production) of CPX-SP. - Microcode: Available through github.com:otcshare/Intel-Generic-Microcode.git. -- ME binary: Not yet available to the public. +- ME binary: Ignition binary will be made public some time after the MP + of CPX-SP. +- ACM binaries: only required for CBnT enablement. ## Payload - LinuxBoot: This is necessary only if you use LinuxBoot as coreboot payload. @@ -48,6 +50,16 @@ To power off/on the host: To connect to console through SOL (Serial Over Lan): sol-util slotx +## Firmware configurations +[ChromeOS VPD] is used to store most of the firmware configurations. +RO_VPD region holds default values, while RW_VPD region holds customized +values. + +VPD variables supported are: +- firmware_version: This variable holds overall firmware version. coreboot + uses that value to populate smbios type 1 version field. +- DeltaLake specific VPDs: check mb/ocp/deltalake/vpd.h. + ## Working features The solution is developed using LinuxBoot payload with Linux kernel 5.2.9, and [u-root] as initramfs. @@ -61,8 +73,12 @@ as initramfs. - Type 8 -- Port Connector Information - Type 9 -- PCI Slot Information - Type 11 -- OEM String + - Type 16 -- Physical Memory Array + - Type 17 -- Memory Device + - Type 19 -- Memory Array Mapped Address - Type 32 -- System Boot Information - Type 38 -- IPMI Device Information + - Type 41 -- Onboard Devices Extended Information - Type 127 -- End-of-Table - BMC integration: - BMC readiness check @@ -71,6 +87,12 @@ as initramfs. - POST complete pin acknowledgement - Check BMC version: ipmidump -device - SEL record generation +- Converged Bootguard and TXT (CBnT) + - TPM + - Bootguard profile 0T + - TXT + - SRTM (verified through tboot) + - memory secret clearance upon ungraceful shutdown - Early serial output - port 80h direct to GPIO - ACPI tables: APIC/DMAR/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT @@ -87,44 +109,41 @@ as initramfs. - Power button - localboot - netboot from IPv6 -- TPM +- basic memory hardware error injection/detection (SMI handler not upstreamed) +- basic PCIe hardware error injection/detection (SMI handler not upstreamed) ## Stress/performance tests passed -- OS warm reboot (300 cycles) -- DC reboot (300 cycles) -- AC reboot (300 cycle) +- OS warm reboot (1000 cycles) +- DC reboot (1000 cycles) +- AC reboot (1000 cycle) - Mprime test (6 hours) - StressAppTest (6 hours) - Ptugen (6 hours) -- MLC (Intel Memory Latency Check) + +## Performance tests on par with traditional firmware +- coremark +- SpecCPU - Linkpack - Iperf(IPv6) - FIO -## Firmware configurations -[ChromeOS VPD] is used to store most of the firmware configurations. -RO_VPD region holds default values, while RW_VPD region holds customized -values. - -VPD variables supported are: -- firmware_version: This variable holds overall firmware version. coreboot - uses that value to populate smbios type 1 version field. -- DeltaLake specific VPDs: check mb/ocp/deltalake/vpd.h. +## Other tests passed +- Power +- Thermal ## Known issues -- spsInfoLinux64 command fail to return ME version. -- fwts test failures related to mtrr. -- kernel error message related to SleepButton ACPI event. +- MLC (Intel Memory Latency Check) and stream performance issue +- HECI access at OS run time: + - spsInfoLinux64 command fail to return ME version + - ptugen command fail to get memory power ## Feature gaps -- SMBIOS: - - Type 16 -- Physical Memory Array - - Type 17 -- Memory Device - - Type 19 -- Memory Array Mapped Address - - Type 41 -- Onboard Devices Extended Information -- Verified measurement through CBnT -- Boot guard of CBnT -- RO_VPD region as well as other RO regions are not write protected. +- flashrom command not able to update ME region +- ACPI APEI tables +- PCIe hotplug, Virtual Pin Ports +- PCIe Live Error Recovery +- RO_VPD region as well as other RO regions are not write protected +- Not able to selectively enable/disable core ## Technology |