diff options
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 5 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/romstage/fsp_params.c | 3 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index afabcf088e..771fc5aaa7 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -554,6 +554,11 @@ struct soc_intel_alderlake_config { * 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16; see enum slew_rate for values */ uint8_t SlowSlewRate[NUM_VR_DOMAINS]; + + /* CNVi DDR RFIM Enable/Disable + * Default 0. Setting this to 1 enable CNVi DDR RFIM. + */ + bool CnviDdrRfim; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 121251e7de..2d631413b2 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -207,6 +207,9 @@ static void fill_fspm_misc_params(FSP_M_CONFIG *m_cfg, /* Skip generation of MBP HOB from FSP. coreboot doesn't consume it */ m_cfg->SkipMbpHob = 1; + + /* CNVi DDR RFI Mitigation */ + m_cfg->CnviDdrRfim = config->CnviDdrRfim; } static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg, |