diff options
| -rw-r--r-- | payloads/libpayload/arch/arm64/cache.c | 4 | ||||
| -rw-r--r-- | payloads/libpayload/include/arm64/arch/cache.h | 11 |
2 files changed, 12 insertions, 3 deletions
diff --git a/payloads/libpayload/arch/arm64/cache.c b/payloads/libpayload/arch/arm64/cache.c index 2ce1cc4a06..799e2d240c 100644 --- a/payloads/libpayload/arch/arm64/cache.c +++ b/payloads/libpayload/arch/arm64/cache.c @@ -120,7 +120,5 @@ void dcache_invalidate_by_mva(void const *addr, size_t len) void cache_sync_instructions(void) { dcache_clean_all(); /* includes trailing DSB (in assembly) */ - iciallu(); /* includes BPIALLU (architecturally) */ - dsb(); - isb(); + icache_invalidate_all(); /* includes leading DSB and trailing ISB */ } diff --git a/payloads/libpayload/include/arm64/arch/cache.h b/payloads/libpayload/include/arm64/arch/cache.h index cfd3109559..757775886c 100644 --- a/payloads/libpayload/include/arm64/arch/cache.h +++ b/payloads/libpayload/include/arm64/arch/cache.h @@ -103,6 +103,17 @@ void cache_sync_instructions(void); /* tlb invalidate all */ void tlb_invalidate_all(void); +/* Invalidate all of the instruction cache for PE to PoU. */ +static inline void icache_invalidate_all(void) +{ + __asm__ __volatile__( + "dsb sy\n\t" + "ic iallu\n\t" + "dsb sy\n\t" + "isb\n\t" + : : : "memory"); +} + /* * Generalized setup/init functions */ |