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-rw-r--r--src/mainboard/asrock/g41c-gs/romstage.c7
-rw-r--r--src/mainboard/asus/p5qc/romstage.c7
-rw-r--r--src/mainboard/asus/p5qpl-am/romstage.c7
-rw-r--r--src/mainboard/foxconn/g41s-k/romstage.c7
-rw-r--r--src/mainboard/gigabyte/ga-g41m-es2l/romstage.c8
-rw-r--r--src/mainboard/intel/dg41wv/romstage.c7
-rw-r--r--src/mainboard/intel/dg43gt/romstage.c7
-rw-r--r--src/mainboard/lenovo/thinkcentre_a58/romstage.c7
-rw-r--r--src/northbridge/intel/x4x/raminit.c7
9 files changed, 7 insertions, 57 deletions
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c
index 64c313c406..88b403ee5c 100644
--- a/src/mainboard/asrock/g41c-gs/romstage.c
+++ b/src/mainboard/asrock/g41c-gs/romstage.c
@@ -25,10 +25,8 @@
#include <superio/winbond/w83627dhg/w83627dhg.h>
#include <superio/winbond/common/winbond.h>
#include <superio/nuvoton/common/nuvoton.h>
-#include <lib.h>
#include <northbridge/intel/x4x/iomap.h>
#include <device/pnp_def.h>
-#include <timestamp.h>
#define SERIAL_DEV_R2 PNP_DEV(0x2e, NCT6776_SP1)
#define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1)
@@ -106,12 +104,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
boot_path = BOOT_PATH_WARM_RESET;
- printk(BIOS_DEBUG, "Initializing memory\n");
- timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(boot_path, spd_addrmap);
- timestamp_add_now(TS_AFTER_INITRAM);
- quick_ram_check();
- printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume);
diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c
index 527f31bcb7..5d585c883d 100644
--- a/src/mainboard/asus/p5qc/romstage.c
+++ b/src/mainboard/asus/p5qc/romstage.c
@@ -23,9 +23,7 @@
#include <cpu/intel/romstage.h>
#include <superio/winbond/w83667hg-a/w83667hg-a.h>
#include <superio/winbond/common/winbond.h>
-#include <lib.h>
#include <northbridge/intel/x4x/iomap.h>
-#include <timestamp.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
@@ -91,12 +89,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
boot_path = BOOT_PATH_WARM_RESET;
- printk(BIOS_DEBUG, "Initializing memory\n");
- timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(boot_path, spd_addrmap);
- timestamp_add_now(TS_AFTER_INITRAM);
- quick_ram_check();
- printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume);
diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c
index 00ab127c67..13e0364b3f 100644
--- a/src/mainboard/asus/p5qpl-am/romstage.c
+++ b/src/mainboard/asus/p5qpl-am/romstage.c
@@ -23,10 +23,8 @@
#include <cpu/intel/romstage.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>
#include <superio/winbond/common/winbond.h>
-#include <lib.h>
#include <northbridge/intel/x4x/iomap.h>
#include <device/pnp_def.h>
-#include <timestamp.h>
#include <halt.h>
#include <cpu/intel/speedstep.h>
#include <cpu/x86/msr.h>
@@ -171,12 +169,7 @@ void mainboard_romstage_entry(unsigned long bist)
halt();
}
- printk(BIOS_DEBUG, "Initializing memory\n");
- timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(boot_path, spd_addrmap);
- timestamp_add_now(TS_AFTER_INITRAM);
- quick_ram_check();
- printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume);
diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c
index 3ebcce3322..9ce9c65c5a 100644
--- a/src/mainboard/foxconn/g41s-k/romstage.c
+++ b/src/mainboard/foxconn/g41s-k/romstage.c
@@ -24,8 +24,6 @@
#include <southbridge/intel/i82801gx/i82801gx.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8720f/it8720f.h>
-#include <lib.h>
-#include <timestamp.h>
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
#define SERIAL_DEV PNP_DEV(0x2e, IT8720F_SP1)
@@ -105,12 +103,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
boot_path = BOOT_PATH_WARM_RESET;
- printk(BIOS_DEBUG, "Initializing memory\n");
- timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(boot_path, spd_addrmap);
- timestamp_add_now(TS_AFTER_INITRAM);
- quick_ram_check();
- printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume);
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
index d3fe50c6fd..0f2b4ffc37 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
@@ -15,7 +15,6 @@
*/
#include <stdint.h>
-#include <stdlib.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -27,9 +26,7 @@
#include <cpu/intel/romstage.h>
#include <superio/ite/it8718f/it8718f.h>
#include <superio/ite/common/ite.h>
-#include <lib.h>
#include <northbridge/intel/x4x/iomap.h>
-#include <timestamp.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
@@ -153,12 +150,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
boot_path = BOOT_PATH_WARM_RESET;
- printk(BIOS_DEBUG, "Initializing memory\n");
- timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(boot_path, spd_addrmap);
- timestamp_add_now(TS_AFTER_INITRAM);
- quick_ram_check();
- printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume);
diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c
index d1bf1bd1e4..d85c559c23 100644
--- a/src/mainboard/intel/dg41wv/romstage.c
+++ b/src/mainboard/intel/dg41wv/romstage.c
@@ -23,10 +23,8 @@
#include <cpu/intel/romstage.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>
#include <superio/winbond/common/winbond.h>
-#include <lib.h>
#include <northbridge/intel/x4x/iomap.h>
#include <device/pnp_def.h>
-#include <timestamp.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
@@ -100,12 +98,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
boot_path = BOOT_PATH_WARM_RESET;
- printk(BIOS_DEBUG, "Initializing memory\n");
- timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(boot_path, spd_addrmap);
- timestamp_add_now(TS_AFTER_INITRAM);
- quick_ram_check();
- printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume);
diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c
index aa8c50ec05..c16160e276 100644
--- a/src/mainboard/intel/dg43gt/romstage.c
+++ b/src/mainboard/intel/dg43gt/romstage.c
@@ -23,9 +23,7 @@
#include <cpu/intel/romstage.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>
#include <superio/winbond/common/winbond.h>
-#include <lib.h>
#include <northbridge/intel/x4x/iomap.h>
-#include <timestamp.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
@@ -93,12 +91,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
boot_path = BOOT_PATH_WARM_RESET;
- printk(BIOS_DEBUG, "Initializing memory\n");
- timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(boot_path, spd_addrmap);
- timestamp_add_now(TS_AFTER_INITRAM);
- quick_ram_check();
- printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume);
diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c
index 31de0e3e9d..b3bd2ed01b 100644
--- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c
+++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c
@@ -22,10 +22,8 @@
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
#include <superio/smsc/smscsuperio/smscsuperio.h>
-#include <lib.h>
#include <northbridge/intel/x4x/iomap.h>
#include <device/pnp_def.h>
-#include <timestamp.h>
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
@@ -86,12 +84,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
boot_path = BOOT_PATH_WARM_RESET;
- printk(BIOS_DEBUG, "Initializing memory\n");
- timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(boot_path, spd_addrmap);
- timestamp_add_now(TS_AFTER_INITRAM);
- quick_ram_check();
- printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume);
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index b3b84d8061..d9fa49d9da 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -22,6 +22,7 @@
#include <arch/cpu.h>
#include <delay.h>
#include <halt.h>
+#include <lib.h>
#include "iomap.h"
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)
#include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */
@@ -34,6 +35,7 @@
#include <device/dram/ddr2.h>
#include <device/dram/ddr3.h>
#include <mrc_cache.h>
+#include <timestamp.h>
#define MRC_CACHE_VERSION 0
@@ -639,6 +641,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
int fast_boot, cbmem_was_inited, cache_not_found;
struct region_device rdev;
+ timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "Setting up RAM controller.\n");
pci_write_config8(PCI_DEV(0, 0, 0), 0xdf, 0xff);
@@ -728,4 +731,8 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
outb(0x6, 0xcf9);
halt();
}
+
+ timestamp_add_now(TS_AFTER_INITRAM);
+ quick_ram_check();
+ printk(BIOS_DEBUG, "Memory initialized\n");
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 09:13:34 +0000