diff options
| -rw-r--r-- | src/soc/amd/common/block/acpi/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/amd/common/block/acpi/acpi.c | 41 | ||||
| -rw-r--r-- | src/soc/amd/common/block/acpi/pm_state.c | 63 | ||||
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/acpi.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/picasso/fch.c | 13 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 13 |
6 files changed, 65 insertions, 69 deletions
diff --git a/src/soc/amd/common/block/acpi/Makefile.inc b/src/soc/amd/common/block/acpi/Makefile.inc index 10e522f064..c6a4725b85 100644 --- a/src/soc/amd/common/block/acpi/Makefile.inc +++ b/src/soc/amd/common/block/acpi/Makefile.inc @@ -7,4 +7,6 @@ ramstage-y += acpi.c postcar-y += acpi.c smm-y += acpi.c +ramstage-y += pm_state.c + endif # CONFIG_SOC_AMD_COMMON_BLOCK_ACPI diff --git a/src/soc/amd/common/block/acpi/acpi.c b/src/soc/amd/common/block/acpi/acpi.c index 572faa51a1..43cc49ccb0 100644 --- a/src/soc/amd/common/block/acpi/acpi.c +++ b/src/soc/amd/common/block/acpi/acpi.c @@ -119,47 +119,6 @@ void acpi_clear_pm_gpe_status(void) acpi_write32(MMIO_ACPI_GPE0_STS, acpi_read32(MMIO_ACPI_GPE0_STS)); } -static int get_index_bit(uint32_t value, uint16_t limit) -{ - uint16_t i; - uint32_t t; - - if (limit >= TOTAL_BITS(uint32_t)) - return -1; - - /* get a mask of valid bits. Ex limit = 3, set bits 0-2 */ - t = (1 << limit) - 1; - if ((value & t) == 0) - return -1; - t = 1; - for (i = 0; i < limit; i++) { - if (value & t) - break; - t <<= 1; - } - return i; -} - -void pm_fill_gnvs(const struct acpi_pm_gpe_state *state) -{ - int index; - struct global_nvs *gnvs = acpi_get_gnvs(); - if (gnvs == NULL) - return; - - index = get_index_bit(state->pm1_sts & state->pm1_en, PM1_LIMIT); - if (index < 0) - gnvs->pm1i = ~0ULL; - else - gnvs->pm1i = index; - - index = get_index_bit(state->gpe0_sts & state->gpe0_en, GPE0_LIMIT); - if (index < 0) - gnvs->gpei = ~0ULL; - else - gnvs->gpei = index; -} - int acpi_get_sleep_type(void) { return acpi_sleep_from_pm1(acpi_read16(MMIO_ACPI_PM1_CNT_BLK)); diff --git a/src/soc/amd/common/block/acpi/pm_state.c b/src/soc/amd/common/block/acpi/pm_state.c new file mode 100644 index 0000000000..5b7567549a --- /dev/null +++ b/src/soc/amd/common/block/acpi/pm_state.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <bootstate.h> +#include <cbmem.h> +#include <soc/acpi.h> +#include <soc/nvs.h> +#include <soc/southbridge.h> +#include <types.h> + +static int get_index_bit(uint32_t value, uint16_t limit) +{ + uint16_t i; + uint32_t t; + + if (limit >= TOTAL_BITS(uint32_t)) + return -1; + + /* get a mask of valid bits. Ex limit = 3, set bits 0-2 */ + t = (1 << limit) - 1; + if ((value & t) == 0) + return -1; + t = 1; + for (i = 0; i < limit; i++) { + if (value & t) + break; + t <<= 1; + } + return i; +} + +static void pm_fill_gnvs(const struct acpi_pm_gpe_state *state) +{ + int index; + struct global_nvs *gnvs = acpi_get_gnvs(); + if (gnvs == NULL) + return; + + index = get_index_bit(state->pm1_sts & state->pm1_en, PM1_LIMIT); + if (index < 0) + gnvs->pm1i = ~0ULL; + else + gnvs->pm1i = index; + + index = get_index_bit(state->gpe0_sts & state->gpe0_en, GPE0_LIMIT); + if (index < 0) + gnvs->gpei = ~0ULL; + else + gnvs->gpei = index; +} + +static void set_nvs_sws(void *unused) +{ + struct chipset_state *state; + + state = cbmem_find(CBMEM_ID_POWER_STATE); + if (state == NULL) + return; + + pm_fill_gnvs(&state->gpe_state); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL); diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index 0512ad69ff..74b8408488 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -32,8 +32,6 @@ void acpi_fill_pm_gpe_state(struct acpi_pm_gpe_state *state); void acpi_pm_gpe_add_events_print_events(const struct acpi_pm_gpe_state *state); /* Clear PM and GPE status registers. */ void acpi_clear_pm_gpe_status(void); -/* Fill GNVS object from PM GPE object. */ -void pm_fill_gnvs(const struct acpi_pm_gpe_state *state); /* * If a system reset is about to be requested, modify the PM1 register so it diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index 7479a35cab..ac5329de1d 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -145,19 +145,6 @@ static void sb_init_acpi_ports(void) PM_ACPI_TIMER_EN_EN); } -static void set_nvs_sws(void *unused) -{ - struct chipset_state *state; - - state = cbmem_find(CBMEM_ID_POWER_STATE); - if (state == NULL) - return; - - pm_fill_gnvs(&state->gpe_state); -} - -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL); - /* * A-Link to AHB bridge, part of the AMBA fabric. These are internal clocks * and unneeded for Raven/Picasso so gate them to save power. diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 1a1dc8ef9f..25781c29b7 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -402,19 +402,6 @@ static void sb_init_acpi_ports(void) PM_ACPI_TIMER_EN_EN); } -static void set_nvs_sws(void *unused) -{ - struct chipset_state *state; - - state = cbmem_find(CBMEM_ID_POWER_STATE); - if (state == NULL) - return; - - pm_fill_gnvs(&state->gpe_state); -} - -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL); - void southbridge_init(void *chip_info) { struct chipset_state *state; |