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| -rw-r--r-- | Documentation/soc/intel/fsp/index.md | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md index 912c44beea..feeb5e9433 100644 --- a/Documentation/soc/intel/fsp/index.md +++ b/Documentation/soc/intel/fsp/index.md @@ -2,6 +2,18 @@ This section contains documentation about Intel-FSP in public domain. +## Integration Guidelines + +Some guiding principles when working on the glue to integrate FSP into +coreboot, e.g. on how to configure a board in devicetree when that affects +the way FSP works: + +* It should be possible to replace FSP based boot with a native coreboot + implementation for a given chipset without touching the mainboard code. +* The devicetree configures coreboot and part of what coreboot does with the + information is setting some FSP UPDs. The devicetree isn't supposed to + directly configure FSP. + ## Bugs As Intel doesn't even list known bugs, they are collected here until those are fixed. If possible a workaround is described here as well. |