diff options
| -rw-r--r-- | src/mainboard/lenovo/x60/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x60/acpi/ac.asl | 44 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x60/acpi/battery.asl | 296 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x60/acpi/beep.asl | 32 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x60/acpi/ec.asl | 101 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x60/acpi/gpe.asl | 0 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl | 63 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x60/acpi/ich7_pci_irqs.asl | 46 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x60/acpi/lid.asl | 37 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x60/acpi/mainboard.asl | 0 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x60/acpi/platform.asl | 206 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x60/acpi/sleepbutton.asl | 25 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x60/acpi/superio.asl | 0 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x60/acpi/thermal.asl | 0 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x60/acpi/video.asl | 51 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x60/dsdt.asl | 56 |
16 files changed, 958 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 262a4b3057..f3239729d8 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_2048 select CHANNEL_XOR_RANDOMIZATION select HAVE_SMI_HANDLER + select HAVE_ACPI_TABLES config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x60/acpi/ac.asl b/src/mainboard/lenovo/x60/acpi/ac.asl new file mode 100644 index 0000000000..cbc84b2365 --- /dev/null +++ b/src/mainboard/lenovo/x60/acpi/ac.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset (0x46), + , 4, + HPAC, 1 +} + +Device(AC) +{ + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_PSR, 0, NotSerialized) + { + return (HPAC) + } + + Method(_STA, 0, NotSerialized) + { + Return (0x0f) + } +} diff --git a/src/mainboard/lenovo/x60/acpi/battery.asl b/src/mainboard/lenovo/x60/acpi/battery.asl new file mode 100644 index 0000000000..7168581604 --- /dev/null +++ b/src/mainboard/lenovo/x60/acpi/battery.asl @@ -0,0 +1,296 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset (0x38), + B0ST, 4, /* Battery 0 state */ + , 1, + B0CH, 1, /* Battery 0 charging */ + B0DI, 1, /* Battery 0 discharging */ + B0PR, 1, /* Battery 0 present */ + Offset (0x39), + B1ST, 4, /* Battery 1 state */ + , 1, + B1CH, 1, /* Battery 1 charging, */ + B1DI, 1, /* Battery 1 discharging,*/ + B1PR, 1 /* Battery 1 present */ +} + +/* EC Registers */ +/* PAGE == 0x00 */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BARC, 16, /* Battery remaining capacity */ + BAFC, 16, /* Battery full charge capacity */ + Offset(0xa8), + BAPR, 16, /* Battery present rate */ + BAVO, 16, /* Battery Voltage */ +} + +/* PAGE == 0x01 */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + , 15, + BAMA, 1, +} + +/* PAGE == 0x02 */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BADC, 16, /* Design Capacity */ + BADV, 16, /* Design voltage */ + , 16, + , 16, + , 16, + BASN, 16, +} + +/* PAGE == 0x04: Battery type */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BATY, 32 +} + + +/* PAGE == 0x05: Battery OEM information */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BAOE, 128 +} + +/* PAGE == 0x06: Battery name */ +Field (ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xa0), + BANA, 128 +} + +/* Arg0: Battery + * Arg1: Battery Status Package + * Arg2: charging + * Arg3: discharging + */ +Method(BSTA, 4, NotSerialized) +{ + Acquire(ECLK, 0xffff) + Store(0, Local0) + Or(1, Arg0, PAGE) + Store(BAMA, Local1) + Store(Arg0, PAGE) /* Battery dynamic information */ + + Store(BAPR, Local2) + + if (Arg2) // charging + { + Or(2, Local0, Local0) + + If (LGreaterEqual (Local2, 0x8000)) { + Store(0, Local2) + } + } + + if (Arg3) // discharging + { + Or(1, Local0, Local0) + Subtract(0x10000, Local2, Local2) + } + + Store(Local0, Index(Arg1, 0x00)) + + if (Local1) { + Multiply (BARC, 10, Index(Arg1, 2)) + Multiply (Local2, BAVO, Local2) + Divide (Local2, 1000, Local3, Index(Arg1, 1)) + } else { + Store(BARC, Index(Arg1, 2)) + Store(Local2, Index(Arg1, 1)) + } + Store(BAVO, Index(Arg1, 3)) + Release(ECLK) + Return (Arg1) +} + +Method(BINF, 2, NotSerialized) +{ + Acquire(ECLK, 0xffff) + Or(1, Arg1, PAGE) /* Battery 0 static information */ + Xor(BAMA, 1, Index(Arg0, 0)) + Store(BAMA, Local0) + Store(Arg1, PAGE) + Store(BAFC, Local2) + Or(2, Arg1, PAGE) + Store(BADC, Local1) + + if (Local0) + { + Multiply (Local1, 10, Local1) + Multiply (Local2, 10, Local2) + } + + Store(Local1, Index(Arg0, 1)) // Design Capacity + Store(Local2, Index(Arg0, 2)) // Last full charge capacity + Store(BADV, Index(Arg0, 4)) // Design Voltage + Divide (Local2, 20, Local0, Index(Arg0, 5)) // Warning capacity + + Store (BASN, Local0) + Name (SERN, Buffer (0x06) { " " }) + Store (4, Local1) + While (Local0) + { + Divide (Local0, 0x0A, Local2, Local0) + Add (Local2, 48, Index (SERN, Local1)) + Decrement (Local1) + } + Store (SERN, Index (Arg0, 10)) // Serial Number + + Or(4, Arg1, PAGE) + Name (TYPE, Buffer() { 0, 0, 0, 0, 0 }) + Store(BATY, TYPE) + Store(TYPE, Index (Arg0, 11)) // Battery type + Or(5, Arg1, PAGE) + Store(BAOE, Index (Arg0, 12)) // OEM information + Or(6, Arg1, PAGE) + Store(BANA, Index (Arg0, 9)) // Model number + Release(ECLK) + Return (Arg0) +} + +Device (BAT0) +{ + Name (_HID, EisaId ("PNP0C0A")) + Name (_UID, 0x00) + Name (_PCL, Package () { \_SB }) + + Name (BATS, Package () + { + 0x00, // 0: PowerUnit: Report in mWh + 0xFFFFFFFF, // 1: Design cap + 0xFFFFFFFF, // 2: Last full charge cap + 0x01, // 3: Battery Technology + 10800, // 4: Design Voltage (mV) + 0x00, // 5: Warning design capacity + 200, // 6: Low design capacity + 1, // 7: granularity1 + 1, // 8: granularity2 + "", // 9: Model number + "", // A: Serial number + "", // B: Battery Type + "" // C: OEM information + }) + + Method (_BIF, 0, NotSerialized) + { + Return (BINF(BATS, 0)) + } + + Name (BATI, Package () + { + 0, // Battery State + // Bit 0 - discharge + // Bit 1 - charge + // Bit 2 - critical state + 0, // Battery present Rate + 0, // Battery remaining capacity + 0 // Battery present voltage + }) + + Method (_BST, 0, NotSerialized) + { + if (B0PR) { + Return (BSTA(0, BATI, B0CH, B0DI)) + } else { + Return (BATS) + } + } + + Method (_STA, 0, NotSerialized) + { + if (B0PR) { + Return (0x1f) + } else { + Return (0x0f) + } + } +} + +Device (BAT1) +{ + Name (_HID, EisaId ("PNP0C0A")) + Name (_UID, 0x00) + Name (_PCL, Package () { \_SB }) + + Name (BATS, Package () + { + 0x00, // 0: PowerUnit: Report in mWh + 0xFFFFFFFF, // 1: Design cap + 0xFFFFFFFF, // 2: Last full charge cap + 0x01, // 3: Battery Technology + 10800, // 4: Design Voltage (mV) + 0x00, // 5: Warning design capacity + 200, // 6: Low design capacity + 1, // 7: granularity1 + 1, // 8: granularity2 + "", // 9: Model number + "", // A: Serial number + "", // B: Battery Type + "" // C: OEM information + }) + + Method (_BIF, 0, NotSerialized) + { + Return (BINF(BATS, 0x10)) + } + + Name (BATI, Package () + { + 0, // Battery State + // Bit 0 - discharge + // Bit 1 - charge + // Bit 2 - critical state + 0, // Battery present Rate + 0, // Battery remaining capacity + 0 // Battery present voltage + }) + + Method (_BST, 0, NotSerialized) + { + if (B1PR) { + Return (BSTA(0x10, BATI, B1CH, B1DI)) + } else { + Return (BATS) + } + } + + Method (_STA, 0, NotSerialized) + { + if (B1PR) { + Return (0x1f) + } else { + Return (0x0f) + } + } +} diff --git a/src/mainboard/lenovo/x60/acpi/beep.asl b/src/mainboard/lenovo/x60/acpi/beep.asl new file mode 100644 index 0000000000..718f41bd37 --- /dev/null +++ b/src/mainboard/lenovo/x60/acpi/beep.asl @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset (0x06), + SNDS, 8 /* Write to this register to generate sound */ + +} + +Method(BEEP, 1, NotSerialized) +{ + Store (Arg0, SNDS) +} diff --git a/src/mainboard/lenovo/x60/acpi/ec.asl b/src/mainboard/lenovo/x60/acpi/ec.asl new file mode 100644 index 0000000000..775fa582ab --- /dev/null +++ b/src/mainboard/lenovo/x60/acpi/ec.asl @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + + Name (_GPE, 28) + Mutex (ECLK, 0) + + OperationRegion(ERAM, EmbeddedControl, 0x00, 0x100) + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x05), + HSPA, 1, + Offset (0x0C), + LEDS, 8, /* LED state */ + Offset (0x3B), + , 1, + KBLT, 1, /* Keyboard Light */ + Offset (0x81), + PAGE, 8 /* Information Page Selector */ + } + + Method (_CRS, 0) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 1, 1) + IO (Decode16, 0x66, 0x66, 1, 1) + }) + Return (ECMD) + } + + Method (LED, 1, NotSerialized) + { + Store(Arg0, LEDS) + } + + Method (_INI, 0, NotSerialized) + { + } + + /* Sleep Button pressed */ + Method(_Q13, 0, NotSerialized) + { + Notify(\_SB.PCI0.LPCB.EC.SLPB, 0x80) + } + + /* Brightness up GPE */ + Method(_Q14, 0, NotSerialized) + { + \DSPC.BRTU () + } + + /* Brightness down GPE */ + Method(_Q15, 0, NotSerialized) + { + \DSPC.BRTD() + } + + /* AC status change: present */ + Method(_Q26, 0, NotSerialized) + { + Notify (AC, 0x80) + Beep(6) + } + + /* AC status change: not present */ + Method(_Q27, 0, NotSerialized) + { + Notify (AC, 0x80) + Beep(6) + } + + +#include "ac.asl" +#include "battery.asl" +#include "sleepbutton.asl" +#include "lid.asl" +#include "beep.asl" +} diff --git a/src/mainboard/lenovo/x60/acpi/gpe.asl b/src/mainboard/lenovo/x60/acpi/gpe.asl new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/src/mainboard/lenovo/x60/acpi/gpe.asl diff --git a/src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl b/src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl new file mode 100644 index 0000000000..e834ae1da9 --- /dev/null +++ b/src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * i945 + */ + + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA + Package() { 0x001bffff, 1, 0, 0x11 }, // Audio + Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge + Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge + Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge + Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge + Package() { 0x001dffff, 0, 0, 0x10 }, // USB + Package() { 0x001dffff, 1, 0, 0x11 }, // USB + Package() { 0x001dffff, 2, 0, 0x12 }, // USB + Package() { 0x001dffff, 3, 0, 0x13 }, // USB + Package() { 0x001fffff, 0, 0, 0x17 }, // LPC + Package() { 0x001fffff, 1, 0, 0x10 }, // IDE + Package() { 0x001fffff, 2, 0, 0x10 } // SATA + }) + } Else { + Return (Package() { + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA + Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // PCI + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // PCI + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // PCI + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // PCI + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 } // SATA + }) + } +} diff --git a/src/mainboard/lenovo/x60/acpi/ich7_pci_irqs.asl b/src/mainboard/lenovo/x60/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000000..548996c54c --- /dev/null +++ b/src/mainboard/lenovo/x60/acpi/ich7_pci_irqs.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x16 }, + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 } + }) + } Else { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 } + }) +} diff --git a/src/mainboard/lenovo/x60/acpi/lid.asl b/src/mainboard/lenovo/x60/acpi/lid.asl new file mode 100644 index 0000000000..2c92ee67e0 --- /dev/null +++ b/src/mainboard/lenovo/x60/acpi/lid.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset (0x46), + , 2, + LIDS , 1 +} + +Device(LID) +{ + Name(_HID, "PNP0C0D") + + Method(_LId, 0, NotSerialized) + { + return (LIDS) + } +} diff --git a/src/mainboard/lenovo/x60/acpi/mainboard.asl b/src/mainboard/lenovo/x60/acpi/mainboard.asl new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/src/mainboard/lenovo/x60/acpi/mainboard.asl diff --git a/src/mainboard/lenovo/x60/acpi/platform.asl b/src/mainboard/lenovo/x60/acpi/platform.asl new file mode 100644 index 0000000000..1cd5c66932 --- /dev/null +++ b/src/mainboard/lenovo/x60/acpi/platform.asl @@ -0,0 +1,206 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* These come from the dynamically created CPU SSDT */ +External(PDC0) +External(PDC1) + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + // Call a trap so SMI can prepare for Sleep as well. + // TRAP(0x55) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + // CPU specific part + + // Notify PCI Express slots in case a card + // was inserted while a sleep state was active. + + // Are we going to S3? + If (LEqual(Arg0, 3)) { + // .. + } + + // Are we going to S4? + If (LEqual(Arg0, 4)) { + // .. + } + + // TODO: Windows XP SP2 P-State restore + + Return(Package(){0,0}) +} + +// Power notification + +External (\_PR_.CPU0, DeviceObj) +External (\_PR_.CPU1, DeviceObj) + +Method (PNOT) +{ + If (MPEN) { + If(And(PDC0, 0x08)) { + Notify (\_PR_.CPU0, 0x80) // _PPC + + If (And(PDC0, 0x10)) { + Sleep(100) + Notify(\_PR_.CPU0, 0x81) // _CST + } + } + + If(And(PDC1, 0x08)) { + Notify (\_PR_.CPU1, 0x80) // _PPC + If (And(PDC1, 0x10)) { + Sleep(100) + Notify(\_PR_.CPU1, 0x81) // _CST + } + } + + } Else { // UP + Notify (\_PR_.CPU0, 0x80) + Sleep(0x64) + Notify(\_PR_.CPU0, 0x81) + } + + // Notify the Batteries + Notify(\_SB.PCI0.LPCB.EC.BAT0, 0x80) // Execute BAT1 _BST + Notify(\_SB.PCI0.LPCB.EC.BAT1, 0x80) // Execute BAT2 _BST +} + +/* System Bus */ + +Scope(\_SB) +{ + /* This method is placed on the top level, so we can make sure it's the + * first executed _INI method. + */ + Method(_INI, 0) + { + /* The DTS data in NVS is probably not up to date. + * Update temperature values and make sure AP thermal + * interrupts can happen + */ + + // TRAP(71) // TODO + + /* Determine the Operating System and save the value in OSYS. + * We have to do this in order to be able to work around + * certain windows bugs. + * + * OSYS value | Operating System + * -----------+------------------ + * 2000 | Windows 2000 + * 2001 | Windows XP(+SP1) + * 2002 | Windows XP SP2 + * 2006 | Windows Vista + * ???? | Windows 7 + */ + + /* Let's assume we're running at least Windows 2000 */ + Store (2000, OSYS) + + If (CondRefOf(_OSI, Local0)) { + /* Linux answers _OSI with "True" for a couple of + * Windows version queries. But unlike Windows it + * needs a Video repost, so let's determine whether + * we're running Linux. + */ + + If (_OSI("Linux")) { + Store (1, LINX) + } + + If (_OSI("Windows 2001")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP2")) { + Store (2002, OSYS) + } + + If (_OSI("Windows 2006")) { + Store (2006, OSYS) + } + } + + /* And the OS workarounds start right after we know what we're + * running: Windows XP SP1 needs to have C-State coordination + * enabled in SMM. + */ + If (LAnd(LEqual(OSYS, 2001), MPEN)) { + // TRAP(61) // TODO + } + + /* SMM power state and C4-on-C3 settings need to be updated */ + // TRAP(43) // TODO + } +} + diff --git a/src/mainboard/lenovo/x60/acpi/sleepbutton.asl b/src/mainboard/lenovo/x60/acpi/sleepbutton.asl new file mode 100644 index 0000000000..c339158b31 --- /dev/null +++ b/src/mainboard/lenovo/x60/acpi/sleepbutton.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device(SLPB) +{ + Name (_HID, EisaId ("PNP0C0E")) +} diff --git a/src/mainboard/lenovo/x60/acpi/superio.asl b/src/mainboard/lenovo/x60/acpi/superio.asl new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/src/mainboard/lenovo/x60/acpi/superio.asl diff --git a/src/mainboard/lenovo/x60/acpi/thermal.asl b/src/mainboard/lenovo/x60/acpi/thermal.asl new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/src/mainboard/lenovo/x60/acpi/thermal.asl diff --git a/src/mainboard/lenovo/x60/acpi/video.asl b/src/mainboard/lenovo/x60/acpi/video.asl new file mode 100644 index 0000000000..c2f9dfb459 --- /dev/null +++ b/src/mainboard/lenovo/x60/acpi/video.asl @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (DSPC) +{ + Name (_ADR, 0x00020001) + OperationRegion (DSPC, PCI_Config, 0x00, 0x100) + Field (DSPC, ByteAcc, NoLock, Preserve) + { + Offset (0xf4), + BRTC, 8 + } + + Method(BRTD, 0, NotSerialized) + { + Store(BRTC, Local0) + if (LGreater (Local0, 15)) + { + Subtract(Local0, 16, Local0) + Store(Local0, BRTC) + } + } + + Method(BRTU, 0, NotSerialized) + { + Store (BRTC, Local0) + if (LLess(Local0, 0xff)) + { + Add (Local0, 16, Local0) + Store(Local0, BRTC) + } + } +} diff --git a/src/mainboard/lenovo/x60/dsdt.asl b/src/mainboard/lenovo/x60/dsdt.asl new file mode 100644 index 0000000000..e3a62a3a19 --- /dev/null +++ b/src/mainboard/lenovo/x60/dsdt.asl @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + + // General Purpose Events + #include "acpi/gpe.asl" + + // mainboard specific devices + #include "acpi/mainboard.asl" + + // Thermal Zone + #include "acpi/thermal.asl" + + Scope (\_SB) { + Device (PCI0) + { + #include "../../../northbridge/intel/i945/acpi/i945.asl" + #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + } + } + + /* Chipset specific sleep states */ + #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" +} |