diff options
| -rw-r--r-- | src/soc/intel/common/block/p2sb/p2sb.c | 50 |
1 files changed, 12 insertions, 38 deletions
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 34b6e06cb5..c968409e0a 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -29,40 +29,14 @@ #define HIDE_BIT (1 << 0) -#if defined(__SIMPLE_DEVICE__) -static pci_devfn_t p2sb_get_device(void) -{ - int devfn = PCH_DEVFN_P2SB; - pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); - - if (dev == PCI_DEV_INVALID) - die_with_post_code(POST_HW_INIT_FAILURE, - "PCH_DEV_P2SB not found!\n"); - - return dev; -} -#else -static struct device *p2sb_get_device(void) -{ - struct device *dev = PCH_DEV_P2SB; - if (!dev) - die_with_post_code(POST_HW_INIT_FAILURE, - "PCH_DEV_P2SB not found!\n"); - - return dev; -} -#endif - -#define P2SB_GET_DEV p2sb_get_device() - void p2sb_enable_bar(void) { /* Enable PCR Base address in PCH */ - pci_write_config32(P2SB_GET_DEV, PCI_BASE_ADDRESS_0, P2SB_BAR); - pci_write_config32(P2SB_GET_DEV, PCI_BASE_ADDRESS_1, 0); + pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, P2SB_BAR); + pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0); /* Enable P2SB MSE */ - pci_write_config8(P2SB_GET_DEV, PCI_COMMAND, + pci_write_config8(PCH_DEV_P2SB, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } @@ -79,7 +53,7 @@ void p2sb_configure_hpet(void) * the High Performance Timer memory address range * selected by bits 1:0 */ - pci_write_config8(P2SB_GET_DEV, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT); + pci_write_config8(PCH_DEV_P2SB, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT); } static void p2sb_set_hide_bit(int hide) @@ -88,18 +62,18 @@ static void p2sb_set_hide_bit(int hide) const uint8_t mask = HIDE_BIT; uint8_t val; - val = pci_read_config8(P2SB_GET_DEV, reg); + val = pci_read_config8(PCH_DEV_P2SB, reg); val &= ~mask; if (hide) val |= mask; - pci_write_config8(P2SB_GET_DEV, reg, val); + pci_write_config8(PCH_DEV_P2SB, reg, val); } void p2sb_unhide(void) { p2sb_set_hide_bit(0); - if (pci_read_config16(P2SB_GET_DEV, PCI_VENDOR_ID) != + if (pci_read_config16(PCH_DEV_P2SB, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL) die_with_post_code(POST_HW_INIT_FAILURE, "Unable to unhide PCH_DEV_P2SB device !\n"); @@ -109,7 +83,7 @@ void p2sb_hide(void) { p2sb_set_hide_bit(1); - if (pci_read_config16(P2SB_GET_DEV, PCI_VENDOR_ID) != + if (pci_read_config16(PCH_DEV_P2SB, PCI_VENDOR_ID) != 0xFFFF) die_with_post_code(POST_HW_INIT_FAILURE, "Unable to hide PCH_DEV_P2SB device !\n"); @@ -119,8 +93,8 @@ static void p2sb_configure_endpoints(int epmask_id, uint32_t mask) { uint32_t reg32; - reg32 = pci_read_config32(P2SB_GET_DEV, PCH_P2SB_EPMASK(epmask_id)); - pci_write_config32(P2SB_GET_DEV, PCH_P2SB_EPMASK(epmask_id), + reg32 = pci_read_config32(PCH_DEV_P2SB, PCH_P2SB_EPMASK(epmask_id)); + pci_write_config32(PCH_DEV_P2SB, PCH_P2SB_EPMASK(epmask_id), reg32 | mask); } @@ -129,8 +103,8 @@ static void p2sb_lock_endpoints(void) uint8_t reg8; /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */ - reg8 = pci_read_config8(P2SB_GET_DEV, PCH_P2SB_E0 + 2); - pci_write_config8(P2SB_GET_DEV, PCH_P2SB_E0 + 2, + reg8 = pci_read_config8(PCH_DEV_P2SB, PCH_P2SB_E0 + 2); + pci_write_config8(PCH_DEV_P2SB, PCH_P2SB_E0 + 2, reg8 | P2SB_E0_MASKLOCK); } |