diff options
| -rw-r--r-- | src/mainboard/asrock/e350m1/mainboard.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index ef9b5e9c50..808c6ee545 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -25,6 +25,7 @@ #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include <southbridge/amd/cimx/cimx_util.h> +#include "SBPLATFORM.h" //#define SMBUS_IO_BASE 0x6000 void set_pcie_reset(void); @@ -54,6 +55,20 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + /* Power off unused clock pins of GPP PCIe devices */ + u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); + /* + * GPP CLK0 connected to unpopulated mini PCIe slot + * GPP CLK1 connected to ethernet chip + */ + write8(misc_mem_clk_cntrl + 0, 0xFF); + /* GPP CLK2 connected to the external USB3 controller */ + write8(misc_mem_clk_cntrl + 1, 0x0F); + write8(misc_mem_clk_cntrl + 2, 0x00); + write8(misc_mem_clk_cntrl + 3, 0x00); + /* SLT_GFX_CLK connected to PCIe slot */ + write8(misc_mem_clk_cntrl + 4, 0xF0); + /* * Initialize ASF registers to an arbitrary address because someone * long ago set things up this way inside the SPD read code. The |