diff options
| -rw-r--r-- | src/soc/intel/jasperlake/chip.h | 12 | ||||
| -rw-r--r-- | src/soc/intel/jasperlake/fsp_params.c | 6 |
2 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 001597e308..18627f6021 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -403,6 +403,18 @@ struct soc_intel_jasperlake_config { */ uint8_t RampDown; + /* + * It controls below soc variables + * + * PchFivrExtV1p05RailEnabledStates + * PchFivrExtVnnRailSxEnabledStates + * PchFivrExtVnnRailEnabledStates + * + * If your platform does not support external vnn power rail please set to 1 + * 1: Disabled ; 0: Enabled + */ + bool disable_external_bypass_vr; + }; typedef struct soc_intel_jasperlake_config config_t; diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 0ad65e408c..4ec9294fac 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -196,6 +196,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->RampDown = config->RampDown; } + if (config->disable_external_bypass_vr) { + params->PchFivrExtV1p05RailEnabledStates = 0; + params->PchFivrExtVnnRailSxEnabledStates = 0; + params->PchFivrExtVnnRailEnabledStates = 0; + } + /* Override/Fill FSP Silicon Param for mainboard */ mainboard_silicon_init_params(params); } |