diff options
| -rw-r--r-- | src/mainboard/google/kahlee/variants/careena/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/google/kahlee/variants/grunt/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/chip.h | 4 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/romstage.c | 9 |
4 files changed, 11 insertions, 10 deletions
diff --git a/src/mainboard/google/kahlee/variants/careena/devicetree.cb b/src/mainboard/google/kahlee/variants/careena/devicetree.cb index ad760b53e3..b541c0305e 100644 --- a/src/mainboard/google/kahlee/variants/careena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/careena/devicetree.cb @@ -21,8 +21,8 @@ chip soc/amd/stoneyridge register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" register "uma_size" = "32 * MiB" register "stapm_percent" = "68" - register "stapm_time" = "2500000" - register "stapm_power" = "7800" + register "stapm_time_ms" = "2500000" + register "stapm_power_mw" = "7800" # Enable I2C0 for audio, USB3 hub at 400kHz register "i2c[0]" = "{ diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb index 8af3f9c356..5a8906b3b1 100644 --- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb @@ -21,8 +21,8 @@ chip soc/amd/stoneyridge register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" register "uma_size" = "32 * MiB" register "stapm_percent" = "80" - register "stapm_time" = "2500000" - register "stapm_power" = "7800" + register "stapm_time_ms" = "2500000" + register "stapm_power_mw" = "7800" # Enable I2C0 for audio, USB3 hub at 400kHz register "i2c[0]" = "{ diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index 8ed8e4d903..320bef0bdf 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -61,8 +61,8 @@ struct soc_amd_stoneyridge_config { u8 i2c_scl_reset; struct dw_i2c_bus_config i2c[STONEY_I2C_DEV_MAX]; u8 stapm_percent; - u32 stapm_time; - u32 stapm_power; + u32 stapm_time_ms; + u32 stapm_power_mw; }; typedef struct soc_amd_stoneyridge_config config_t; diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 555e901501..ed83e1ee1d 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -235,12 +235,13 @@ void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly) } cfg = dev->chip_info; platform = &InitEarly->PlatformConfig; - if ((cfg->stapm_percent) && (cfg->stapm_time) && (cfg->stapm_power)) { + if ((cfg->stapm_percent) && (cfg->stapm_time_ms) && + (cfg->stapm_power_mw)) { platform->PlatStapmConfig.CfgStapmScalar = cfg->stapm_percent; platform->PlatStapmConfig.CfgStapmTimeConstant = - cfg->stapm_time; - platform->PkgPwrLimitDC = cfg->stapm_power; - platform->PkgPwrLimitAC = cfg->stapm_power; + cfg->stapm_time_ms; + platform->PkgPwrLimitDC = cfg->stapm_power_mw; + platform->PkgPwrLimitAC = cfg->stapm_power_mw; platform->PlatStapmConfig.CfgStapmBoost = StapmBoostEnabled; } } |