diff options
| -rw-r--r-- | src/mainboard/google/fizz/Kconfig | 22 | ||||
| -rw-r--r-- | src/mainboard/google/fizz/devicetree.cb | 14 | ||||
| -rw-r--r-- | src/mainboard/google/fizz/gpio.h | 21 | ||||
| -rw-r--r-- | src/mainboard/google/fizz/mainboard.c | 10 |
4 files changed, 60 insertions, 7 deletions
diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index 2d2e6b78c0..da6e67465b 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -13,12 +13,21 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_USES_FSP2_0 select NO_FADT_8042 select SOC_INTEL_KABYLAKE + select FIZZ_USE_I2C_TPM select GENERIC_SPD_BIN config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC +config DRIVER_TPM_I2C_BUS + depends on FIZZ_USE_I2C_TPM + default 0x1 + +config DRIVER_TPM_I2C_ADDR + depends on FIZZ_USE_I2C_TPM + default 0x50 + config GBB_HWID string depends on CHROMEOS @@ -47,4 +56,17 @@ config DIMM_MAX config DIMM_SPD_SIZE int default 512 + +# Select this option to enable use of cr50 I2C TPM on fizz. +config FIZZ_USE_I2C_TPM + bool + default n + select I2C_TPM + select MAINBOARD_HAS_I2C_TPM_CR50 + select TPM2 + +config TPM_TIS_ACPI_INTERRUPT + int + default 64 # GPE0_DW2_00 (GPP_E0) + endif diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index ff2ec7f86d..abd5452f21 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -181,6 +181,12 @@ chip soc/intel/skylake register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3" # Debug register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio + # Configure I2C1 for cr50 TPM. Early init is required to set up a BAR + # for TPM communication before memory is up. + register "i2c[1]" = "{ + .early_init = 1, + }" + # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -214,7 +220,13 @@ chip soc/intel/skylake device pci 14.2 on end # Thermal Subsystem device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 + device pci 15.1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" + device i2c 50 on end + end + end # I2C #1 device pci 15.2 on end # I2C #2 device pci 15.3 off end # I2C #3 diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h index ced33e97b0..9f7da49ed4 100644 --- a/src/mainboard/google/fizz/gpio.h +++ b/src/mainboard/google/fizz/gpio.h @@ -108,8 +108,15 @@ static const struct pad_config gpio_table[] = { /* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* SKU_ID3 */ /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), -/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), -/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), +#if IS_ENABLED(CONFIG_FIZZ_USE_I2C_TPM) +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, + NF1), /* PCH_I2C1_H1_3V3_SDA */ +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, + NF1), /* PCH_I2C1_H1_3V3_SCL */ +#else +/* I2C1_SDA */ PAD_CFG_NC(GPP_C18), +/* I2C1_SCL */ PAD_CFG_NC(GPP_C19), +#endif /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP309 */ @@ -231,10 +238,12 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { -/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, - NF1), /* PCH_I2C2_H1_3V3_SDA */ -/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, - NF1), /* PCH_I2C2_H1_3V3_SCL */ +#if IS_ENABLED(CONFIG_FIZZ_USE_I2C_TPM) +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, + NF1), /* PCH_I2C1_H1_3V3_SDA */ +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, + NF1), /* PCH_I2C1_H1_3V3_SCL */ +#endif /* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* H1_PCH_INT_ODL */ /* Ensure UART pins are in native mode for H1. */ diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index d515d29c43..5346276d35 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -17,6 +17,7 @@ #include <console/console.h> #include <device/device.h> #include <ec/ec.h> +#include <soc/pci_devs.h> #include <vendorcode/google/chromeos/chromeos.h> static void mainboard_init(device_t dev) @@ -26,8 +27,17 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { + device_t tpm; + dev->ops->init = mainboard_init; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + + /* Disable unused interface for TPM. */ + if (!IS_ENABLED(CONFIG_FIZZ_USE_I2C_TPM)) { + tpm = PCH_DEV_I2C1; + if (tpm) + tpm->enabled = 0; + } } struct chip_operations mainboard_ops = { |