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-rw-r--r--src/mainboard/asus/p5qc/Kconfig10
-rw-r--r--src/mainboard/asus/p5qc/Kconfig.name3
-rw-r--r--src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb127
-rw-r--r--src/mainboard/asus/p5qc/variants/p5ql_pro/gpio.c158
4 files changed, 296 insertions, 2 deletions
diff --git a/src/mainboard/asus/p5qc/Kconfig b/src/mainboard/asus/p5qc/Kconfig
index 8661fd6ccb..9c147875f1 100644
--- a/src/mainboard/asus/p5qc/Kconfig
+++ b/src/mainboard/asus/p5qc/Kconfig
@@ -14,7 +14,7 @@
# GNU General Public License for more details.
#
-if BOARD_ASUS_P5QC || BOARD_ASUS_P5Q_PRO
+if BOARD_ASUS_P5QC || BOARD_ASUS_P5Q_PRO || BOARD_ASUS_P5QL_PRO
config BOARD_SPECIFIC_OPTIONS
def_bool y
@@ -38,11 +38,13 @@ config VARIANT_DIR
string
default "p5qc" if BOARD_ASUS_P5QC
default "p5q_pro" if BOARD_ASUS_P5Q_PRO
+ default "p5ql_pro" if BOARD_ASUS_P5QL_PRO
config MAINBOARD_PART_NUMBER
string
default "P5QC" if BOARD_ASUS_P5QC
default "P5Q PRO" if BOARD_ASUS_P5Q_PRO
+ default "P5QL PRO" if BOARD_ASUS_P5QL_PRO
config DEVICETREE
string
@@ -50,6 +52,7 @@ config DEVICETREE
config GPIO_C
string
+ default "variants/p5ql_pro/gpio.c" if BOARD_ASUS_P5QL_PRO
default "gpio.c"
config MAX_CPUS
@@ -59,8 +62,11 @@ config MAX_CPUS
# The MARVELL IDE controller delays SeaBIOS a lot and results in an unbootable
# bogus disk. Compiling SeaBIOS without ATA support is a workaround.
+# The Asus P5QL PRO's Marvell controller (88SE6102-NNC2) does not need this, apparently.
+
config PAYLOAD_CONFIGFILE
string
+ default "" if PAYLOAD_SEABIOS && BOARD_ASUS_P5QL_PRO
default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" if PAYLOAD_SEABIOS
-endif # BOARD_ASUS_P5QC
+endif # BOARD_ASUS_P5Q*
diff --git a/src/mainboard/asus/p5qc/Kconfig.name b/src/mainboard/asus/p5qc/Kconfig.name
index a4c6e4892c..2a3503690f 100644
--- a/src/mainboard/asus/p5qc/Kconfig.name
+++ b/src/mainboard/asus/p5qc/Kconfig.name
@@ -3,3 +3,6 @@ config BOARD_ASUS_P5QC
config BOARD_ASUS_P5Q_PRO
bool "P5Q PRO"
+
+config BOARD_ASUS_P5QL_PRO
+ bool "P5QL PRO"
diff --git a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb
new file mode 100644
index 0000000000..c596a42244
--- /dev/null
+++ b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb
@@ -0,0 +1,127 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+# Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+chip northbridge/intel/x4x # Northbridge
+ device cpu_cluster 0 on # APIC cluster
+ chip cpu/intel/socket_LGA775
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_1067x # CPU
+ device lapic 0xACAC off end
+ end
+ end
+ device domain 0 on # PCI domain
+ device pci 0.0 on end # Host Bridge
+ device pci 1.0 on end # PEG
+ device pci 2.0 off end # Integrated graphics controller
+ device pci 2.1 off end # Integrated graphics controller 2
+ device pci 3.0 off end # ME
+ device pci 3.1 off end # ME
+ device pci 3.2 off end # ME
+ device pci 3.3 off end # ME
+ device pci 6.0 off end # PEG 2
+ chip southbridge/intel/i82801jx # Southbridge
+ register "gpe0_en" = "0x40"
+
+ # Set AHCI mode.
+ register "sata_port_map" = "0x3f"
+ register "sata_clock_request" = "0"
+ register "sata_traffic_monitor" = "0"
+
+ # Enable PCIe ports 0,2,3 as slots.
+ register "pcie_slot_implemented" = "0x31"
+
+ device pci 19.0 off end # GBE
+ device pci 1a.0 on end # USB
+ device pci 1a.1 on end # USB
+ device pci 1a.2 on end # USB
+ device pci 1a.7 on end # USB
+ device pci 1b.0 on end # Audio
+ device pci 1c.0 on end # PCIe 1 PCIe x1 Slot #1
+ device pci 1c.1 on end # PCIe 2 PCIe x1 Slot #2
+ device pci 1c.2 off end # PCIe 3
+ device pci 1c.3 off end # PCIe 4
+ device pci 1c.4 on end # PCIe 5 Marvell IDE
+ device pci 1c.5 on end # PCIe 6 Atheros LAN
+ device pci 1d.0 on end # USB
+ device pci 1d.1 on end # USB
+ device pci 1d.2 on end # USB
+ device pci 1d.7 on end # USB
+ device pci 1e.0 on end # PCI bridge
+ device pci 1f.0 on # LPC bridge
+ chip superio/winbond/w83667hg-a # Super I/O
+ device pnp 2e.0 on # FDC
+ # Global registers
+ irq 0x2a = 0x30
+ irq 0x2c = 0x22
+ irq 0x2d = 0x00
+ io 0x60 = 0x3f0
+ irq 0x70 = 0x06
+ end
+ device pnp 2e.1 off end # LPT1
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off end # COM2
+ device pnp 2e.5 on # PS/2 keyboard & mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.106 off end # SPI1
+ device pnp 2e.107 off end # GPIO6
+ device pnp 2e.207 off end # GPIO7
+ device pnp 2e.307 on # GPIO8
+ irq 0xe4 = 0xfb
+ irq 0xe5 = 0x82
+ end
+ device pnp 2e.407 off end # GPIO9
+ device pnp 2e.8 off end # WDT
+ device pnp 2e.108 off end # GPIO1
+ device pnp 2e.9 off end # GPIO2
+ device pnp 2e.109 on end # GPIO3
+ device pnp 2e.209 on # GPIO4
+ irq 0xf0 = 0xff
+ irq 0xfe = 0x07
+ end
+ device pnp 2e.309 on end # GPIO5
+ device pnp 2e.a on # ACPI
+ irq 0xe4 = 0x10 # 3VSBSW# enable
+ irq 0xe5 = 0x02
+ irq 0xf2 = 0xfc
+ end
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 0x0
+ # IRQ purposefully not assigned to prevent lockups
+ end
+ device pnp 2e.c on end # PECI
+ device pnp 2e.d on end # VID_BUSSEL
+ device pnp 2e.f on end # GPIO_PP_OD
+ end
+ end
+ device pci 1f.1 off end # PATA/IDE
+ device pci 1f.2 on end # SATA
+ device pci 1f.3 on end # SMbus
+ device pci 1f.4 off end
+ device pci 1f.5 off end # IDE
+ device pci 1f.6 on end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/asus/p5qc/variants/p5ql_pro/gpio.c b/src/mainboard/asus/p5qc/variants/p5ql_pro/gpio.c
new file mode 100644
index 0000000000..8775e1ee61
--- /dev/null
+++ b/src/mainboard/asus/p5qc/variants/p5ql_pro/gpio.c
@@ -0,0 +1,158 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_GPIO,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_GPIO,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio1 = GPIO_DIR_OUTPUT,
+ .gpio2 = GPIO_DIR_OUTPUT,
+ .gpio3 = GPIO_DIR_OUTPUT,
+ .gpio4 = GPIO_DIR_OUTPUT,
+ .gpio5 = GPIO_DIR_OUTPUT,
+ .gpio6 = GPIO_DIR_OUTPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_OUTPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_OUTPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_OUTPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_OUTPUT,
+ .gpio18 = GPIO_DIR_OUTPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio20 = GPIO_DIR_OUTPUT,
+ .gpio21 = GPIO_DIR_OUTPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio23 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio1 = GPIO_LEVEL_HIGH,
+ .gpio2 = GPIO_LEVEL_HIGH,
+ .gpio3 = GPIO_LEVEL_HIGH,
+ .gpio4 = GPIO_LEVEL_HIGH,
+ .gpio5 = GPIO_LEVEL_HIGH,
+ .gpio6 = GPIO_LEVEL_HIGH,
+ .gpio9 = GPIO_LEVEL_LOW,
+ .gpio11 = GPIO_LEVEL_HIGH,
+ .gpio12 = GPIO_LEVEL_LOW,
+ .gpio14 = GPIO_LEVEL_HIGH,
+ .gpio17 = GPIO_LEVEL_HIGH,
+ .gpio18 = GPIO_LEVEL_HIGH,
+ .gpio20 = GPIO_LEVEL_HIGH,
+ .gpio21 = GPIO_LEVEL_HIGH,
+ .gpio22 = GPIO_LEVEL_HIGH,
+ .gpio23 = GPIO_LEVEL_HIGH,
+ .gpio27 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio7 = GPIO_INVERT,
+ .gpio10 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio60 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_OUTPUT,
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_OUTPUT,
+ .gpio37 = GPIO_DIR_OUTPUT,
+ .gpio38 = GPIO_DIR_OUTPUT,
+ .gpio39 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_OUTPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio56 = GPIO_DIR_OUTPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_HIGH,
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio34 = GPIO_LEVEL_LOW,
+ .gpio35 = GPIO_LEVEL_LOW,
+ .gpio36 = GPIO_LEVEL_HIGH,
+ .gpio37 = GPIO_LEVEL_HIGH,
+ .gpio38 = GPIO_LEVEL_HIGH,
+ .gpio39 = GPIO_LEVEL_HIGH,
+ .gpio48 = GPIO_LEVEL_LOW,
+ .gpio49 = GPIO_LEVEL_HIGH,
+ .gpio56 = GPIO_LEVEL_HIGH,
+ .gpio57 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 05:08:07 +0000