diff options
| -rw-r--r-- | src/soc/amd/cezanne/chip.h | 39 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/fsp_m_params.c | 44 |
2 files changed, 83 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index af78ddfd9a..7753ab8623 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -27,6 +27,45 @@ struct soc_amd_cezanne_config { DOWNCORE_7 = 10, /* Run with 7 physical cores */ } downcore_mode; bool disable_smt; /* disable second thread on all physical cores */ + + uint8_t stt_control; + uint8_t stt_pcb_sensor_count; + uint16_t stt_min_limit; + uint16_t stt_m1; + uint16_t stt_m2; + uint16_t stt_m3; + uint16_t stt_m4; + uint16_t stt_m5; + uint16_t stt_m6; + uint16_t stt_c_apu; + uint16_t stt_c_gpu; + uint16_t stt_c_hs2; + uint16_t stt_alpha_apu; + uint16_t stt_alpha_gpu; + uint16_t stt_alpha_hs2; + uint16_t stt_skin_temp_apu; + uint16_t stt_skin_temp_gpu; + uint16_t stt_skin_temp_hs2; + uint16_t stt_error_coeff; + uint16_t stt_error_rate_coefficient; + + uint8_t stapm_boost; + uint32_t stapm_time_constant; + uint32_t apu_only_sppt_limit; + uint32_t sustained_power_limit; + uint32_t fast_ppt_limit; + uint32_t slow_ppt_limit; + + uint8_t smartshift_enable; + + uint8_t system_configuration; + + uint8_t cppc_ctrl; + uint8_t cppc_perf_limit_max_range; + uint8_t cppc_perf_limit_min_range; + uint8_t cppc_epp_max_range; + uint8_t cppc_epp_min_range; + uint8_t cppc_preferred_cores; }; #endif /* CEZANNE_CHIP_H */ diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index baf4ca8b85..9d4159d85b 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -69,5 +69,49 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->ccx_down_core_mode = config->downcore_mode; mcfg->ccx_disable_smt = config->disable_smt; + /* when stt_control isn't 1, FSP will ignore the other stt values */ + mcfg->stt_control = config->stt_control; + mcfg->stt_pcb_sensor_count = config->stt_pcb_sensor_count; + mcfg->stt_min_limit = config->stt_min_limit; + mcfg->stt_m1 = config->stt_m1; + mcfg->stt_m2 = config->stt_m2; + mcfg->stt_m3 = config->stt_m3; + mcfg->stt_m4 = config->stt_m4; + mcfg->stt_m5 = config->stt_m5; + mcfg->stt_m6 = config->stt_m6; + mcfg->stt_c_apu = config->stt_c_apu; + mcfg->stt_c_gpu = config->stt_c_gpu; + mcfg->stt_c_hs2 = config->stt_c_hs2; + mcfg->stt_alpha_apu = config->stt_alpha_apu; + mcfg->stt_alpha_gpu = config->stt_alpha_gpu; + mcfg->stt_alpha_hs2 = config->stt_alpha_hs2; + mcfg->stt_skin_temp_apu = config->stt_skin_temp_apu; + mcfg->stt_skin_temp_gpu = config->stt_skin_temp_gpu; + mcfg->stt_skin_temp_hs2 = config->stt_skin_temp_hs2; + mcfg->stt_error_coeff = config->stt_error_coeff; + mcfg->stt_error_rate_coefficient = config->stt_error_rate_coefficient; + + /* all following fields being 0 is a valid config */ + mcfg->stapm_boost = config->stapm_boost; + mcfg->stapm_time_constant = config->stapm_time_constant; + mcfg->apu_only_sppt_limit = config->apu_only_sppt_limit; + mcfg->sustained_power_limit = config->sustained_power_limit; + mcfg->fast_ppt_limit = config->fast_ppt_limit; + mcfg->slow_ppt_limit = config->slow_ppt_limit; + + /* 0 is default */ + mcfg->smartshift_enable = config->smartshift_enable; + + /* 0 is default */ + mcfg->system_configuration = config->system_configuration; + + /* when cppc_ctrl is 0 the other values won't be used */ + mcfg->cppc_ctrl = config->cppc_ctrl; + mcfg->cppc_perf_limit_max_range = config->cppc_perf_limit_max_range; + mcfg->cppc_perf_limit_min_range = config->cppc_perf_limit_min_range; + mcfg->cppc_epp_max_range = config->cppc_epp_max_range; + mcfg->cppc_epp_min_range = config->cppc_epp_min_range; + mcfg->cppc_preferred_cores = config->cppc_preferred_cores; + fsp_fill_pcie_ddi_descriptors(mcfg); } |