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-rw-r--r--src/mainboard/asrock/b85m_pro4/romstage.c13
-rw-r--r--src/mainboard/asrock/h81m-hds/romstage.c9
-rw-r--r--src/mainboard/google/beltino/romstage.c9
-rw-r--r--src/mainboard/google/slippy/romstage.c9
-rw-r--r--src/mainboard/intel/baskingridge/romstage.c13
-rw-r--r--src/mainboard/lenovo/t440p/romstage.c8
-rw-r--r--src/mainboard/supermicro/x10slm-f/romstage.c13
-rw-r--r--src/northbridge/intel/haswell/raminit.h4
-rw-r--r--src/northbridge/intel/haswell/romstage.c3
9 files changed, 61 insertions, 20 deletions
diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c
index f625824a8c..6a71abbe30 100644
--- a/src/mainboard/asrock/b85m_pro4/romstage.c
+++ b/src/mainboard/asrock/b85m_pro4/romstage.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <stdint.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h>
@@ -16,12 +17,16 @@ void mainboard_config_rcba(void)
RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
}
+void mb_get_spd_map(uint8_t spd_map[4])
+{
+ spd_map[0] = 0xa0;
+ spd_map[1] = 0xa2;
+ spd_map[2] = 0xa4;
+ spd_map[3] = 0xa6;
+}
+
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->spd_addresses[0] = 0xa0;
- pei_data->spd_addresses[1] = 0xa2;
- pei_data->spd_addresses[2] = 0xa4;
- pei_data->spd_addresses[3] = 0xa6;
pei_data->ec_present = 0;
pei_data->gbe_enable = 1;
diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c
index cfefdda6de..0573b6b171 100644
--- a/src/mainboard/asrock/h81m-hds/romstage.c
+++ b/src/mainboard/asrock/h81m-hds/romstage.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <stdint.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h>
@@ -16,10 +17,14 @@ void mainboard_config_rcba(void)
RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
}
+void mb_get_spd_map(uint8_t spd_map[4])
+{
+ spd_map[0] = 0xa0;
+ spd_map[2] = 0xa4;
+}
+
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->spd_addresses[0] = 0xa0;
- pei_data->spd_addresses[2] = 0xa4;
pei_data->ec_present = 0;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c
index 839cd6c743..8410d04923 100644
--- a/src/mainboard/google/beltino/romstage.c
+++ b/src/mainboard/google/beltino/romstage.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <stdint.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h>
@@ -39,10 +40,14 @@ void mainboard_config_rcba(void)
RCBA16(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */
}
+void mb_get_spd_map(uint8_t spd_map[4])
+{
+ spd_map[0] = 0xa0;
+ spd_map[2] = 0xa4;
+}
+
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->spd_addresses[0] = 0xa0;
- pei_data->spd_addresses[2] = 0xa4;
pei_data->ec_present = 0;
pei_data->dq_pins_interleaved = 1;
pei_data->usb_xhci_on_resume = 1;
diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c
index e5719448e4..47bcb477f5 100644
--- a/src/mainboard/google/slippy/romstage.c
+++ b/src/mainboard/google/slippy/romstage.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <stdint.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h>
@@ -40,10 +41,14 @@ void mainboard_config_rcba(void)
RCBA16(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */
}
+void mb_get_spd_map(uint8_t spd_map[4])
+{
+ spd_map[0] = 0xff;
+ spd_map[2] = 0xff;
+}
+
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->spd_addresses[0] = 0xff;
- pei_data->spd_addresses[2] = 0xff;
pei_data->ec_present = 1;
pei_data->usb_xhci_on_resume = 1;
diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c
index 73fc54ecad..564177553d 100644
--- a/src/mainboard/intel/baskingridge/romstage.c
+++ b/src/mainboard/intel/baskingridge/romstage.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <stdint.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h>
@@ -40,12 +41,16 @@ void mainboard_config_rcba(void)
RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
}
+void mb_get_spd_map(uint8_t spd_map[4])
+{
+ spd_map[0] = 0xa0;
+ spd_map[1] = 0xa2;
+ spd_map[2] = 0xa4;
+ spd_map[3] = 0xa6;
+}
+
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->spd_addresses[0] = 0xa0;
- pei_data->spd_addresses[1] = 0xa2;
- pei_data->spd_addresses[2] = 0xa4;
- pei_data->spd_addresses[3] = 0xa6;
pei_data->ec_present = 0;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c
index 36787603bf..e83530a8ea 100644
--- a/src/mainboard/lenovo/t440p/romstage.c
+++ b/src/mainboard/lenovo/t440p/romstage.c
@@ -40,10 +40,14 @@ void mb_late_romstage_setup(void)
}
}
+void mb_get_spd_map(uint8_t spd_map[4])
+{
+ spd_map[0] = 0xa0;
+ spd_map[2] = 0xa2;
+}
+
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->spd_addresses[0] = 0xa0;
- pei_data->spd_addresses[2] = 0xa2;
pei_data->ec_present = 1;
pei_data->gbe_enable = 1;
diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c
index 26f820a5b5..036a89c805 100644
--- a/src/mainboard/supermicro/x10slm-f/romstage.c
+++ b/src/mainboard/supermicro/x10slm-f/romstage.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <stdint.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h>
@@ -16,12 +17,16 @@ void mainboard_config_rcba(void)
RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
}
+void mb_get_spd_map(uint8_t spd_map[4])
+{
+ spd_map[0] = 0xa0;
+ spd_map[1] = 0xa2;
+ spd_map[2] = 0xa4;
+ spd_map[3] = 0xa6;
+}
+
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- pei_data->spd_addresses[0] = 0xa0;
- pei_data->spd_addresses[1] = 0xa2;
- pei_data->spd_addresses[2] = 0xa4;
- pei_data->spd_addresses[3] = 0xa6;
pei_data->ec_present = 0;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h
index 140ea2088d..adf53ea4b4 100644
--- a/src/northbridge/intel/haswell/raminit.h
+++ b/src/northbridge/intel/haswell/raminit.h
@@ -3,11 +3,15 @@
#ifndef RAMINIT_H
#define RAMINIT_H
+#include <stdint.h>
#include "pei_data.h"
/* Optional function to copy SPD data for on-board memory */
void copy_spd(struct pei_data *peid);
+/* Mainboard callback to fill in the SPD addresses in MRC format */
+void mb_get_spd_map(uint8_t spd_map[4]);
+
/* Necessary function to initialize pei_data with mainboard-specific settings */
void mainboard_fill_pei_data(struct pei_data *pei_data);
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
index 40b7b879d1..2961299e7d 100644
--- a/src/northbridge/intel/haswell/romstage.c
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -87,6 +87,9 @@ void mainboard_romstage_entry(void)
/* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */
pei_data.boot_mode = wake_from_s3 ? 2 : 0;
+ /* Obtain the SPD addresses from mainboard code */
+ mb_get_spd_map(pei_data.spd_addresses);
+
/* Calculate unimplemented DIMM slots for each channel */
pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0);
pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1);
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-05 04:51:40 +0000