diff options
| -rw-r--r-- | src/mainboard/starlabs/starbook/Kconfig | 21 | ||||
| -rw-r--r-- | src/mainboard/starlabs/starbook/variants/adl/devicetree.cb | 4 |
2 files changed, 0 insertions, 25 deletions
diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig index 5ad7e2747f..b49a86d4b3 100644 --- a/src/mainboard/starlabs/starbook/Kconfig +++ b/src/mainboard/starlabs/starbook/Kconfig @@ -147,30 +147,9 @@ config EDK2_BOOTSPLASH_FILE string default "3rdparty/blobs/mainboard/starlabs/Logo.bmp" -config PCIEXP_ASPM - bool - default n - help - FSP is already taking care of ASPM, which is configured through the devicetree in coreboot - on Alderlake Platforms. Disable it to save some boot time. - config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS default 32 -config PCIEXP_L1_SUB_STATE - bool - default n - help - Enabling PCIe L1 sub states is already done in FSP. - Disable it to save some boot time. - -config PCIEXP_CLK_PM - bool - default n - help - Enabling PCIe clock power management is already done in FSP. - Disable it to save some boot time - config SOC_INTEL_CSE_SEND_EOP_EARLY default n if BOARD_STARLABS_STARBOOK_ADL diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index 5c54f4da35..298ec199b2 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -100,8 +100,6 @@ chip soc/intel/alderlake .clk_src = 2, .clk_req = 2, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort" @@ -119,8 +117,6 @@ chip soc/intel/alderlake .clk_src = 1, .clk_req = 1, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypeM2Socket3" |