diff options
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb | 120 |
1 files changed, 120 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb index a5e2217fef..c05658a090 100644 --- a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb @@ -1,4 +1,124 @@ chip soc/intel/alderlake + + # GPE configuration + register "pmc_gpe0_dw0" = "GPP_A" + register "pmc_gpe0_dw1" = "GPP_E" + register "pmc_gpe0_dw2" = "GPP_F" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + # S0ix enable + register "s0ix_enable" = "1" + + # DPTF enable + register "dptf_enable" = "1" + + register "tcc_offset" = "10" # TCC of 90 + + # Enable CNVi BT + register "cnvi_bt_core" = "true" + + register "usb2_ports[0]" = "USB2_PORT_EMPTY" + register "usb2_ports[1]" = "USB2_PORT_EMPTY" + register "usb2_ports[2]" = "USB2_PORT_EMPTY" + register "usb2_ports[3]" = "USB2_PORT_EMPTY" + register "usb2_ports[4]" = "USB2_PORT_EMPTY" + register "usb2_ports[5]" = "USB2_PORT_EMPTY" + register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_EMPTY" + + register "usb3_ports[0]" = "USB3_PORT_EMPTY" + register "usb3_ports[1]" = "USB3_PORT_EMPTY" + register "usb3_ports[2]" = "USB3_PORT_EMPTY" + register "usb3_ports[3]" = "USB3_PORT_EMPTY" + + register "tcss_ports[0]" = "TCSS_PORT_EMPTY" + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" + register "tcss_ports[2]" = "TCSS_PORT_EMPTY" + register "tcss_ports[3]" = "TCSS_PORT_EMPTY" + + register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_50_MS" + register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_1S" + register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S" + register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS" + register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S" + + # HD Audio + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" + + # FIVR RFI Spread Spectrum 1.5% + register "fivr_spread_spectrum" = "FIVR_SS_1_5" + + # Disable C state auto-demotion for all brya baseboards + register "disable_c1_state_auto_demotion" = "1" + + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + device domain 0 on + # The timing values can be derived from datasheet of display panel + # You can use EDID string to identify the type of display on the board + # use below command to get display info from EDID + # strings /sys/devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/edid + + # refer to display PRM document (Volume 2b: Command Reference: Registers) + # for more info on display control registers + # https://01.org/linuxgraphics/documentation/hardware-specification-prms + #+-----------------------------+---------------------------------------+-----+ + #| Intel docs | devicetree.cb | eDP | + #+-----------------------------+---------------------------------------+-----+ + #| Power up delay | `gpu_panel_power_up_delay` | T3 | + #+-----------------------------+---------------------------------------+-----+ + #| Power on to backlight on | `gpu_panel_power_backlight_on_delay` | T7 | + #+-----------------------------+---------------------------------------+-----+ + #| Power Down delay | `gpu_panel_power_down_delay` | T10 | + #+-----------------------------+---------------------------------------+-----+ + #| Backlight off to power down | `gpu_panel_power_backlight_off_delay` | T9 | + #+-----------------------------+---------------------------------------+-----+ + #| Power Cycle Delay | `gpu_panel_power_cycle_delay` | T12 | + #+-----------------------------+---------------------------------------+-----+ + device ref igpu on + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" + end + device ref dtt on end + device ref tcss_xhci on end + device ref xhci on end + device ref shared_sram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + device ref heci1 on end + device ref sata on end + device ref uart0 on end + device ref gspi1 on end + device ref pch_espi on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device ref hda on end end end |