diff options
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h | 2 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h | 60 |
2 files changed, 32 insertions, 30 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h index 76c8fd6394..1f55fda5ac 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -1527,7 +1527,7 @@ typedef struct { UINT8 PvdRatioThreshold; /** Offset 0x045B - Support Unlimited ICCMAX - Support Unlimited ICCMAX more than maximum value 512A; <b>0: Disabled</b>; 1: Enabled. + DEPRECATED $EN_DIS **/ UINT8 UnlimitedIccMax; diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h index d689bd8c3b..14127fce54 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h @@ -1601,9 +1601,11 @@ typedef struct { **/ UINT16 SmbiosType4MaxSpeedOverride; -/** Offset 0x06C2 - Reserved +/** Offset 0x06C2 - Current root mean square + PCODE MMIO Mailbox: Current root mean square; <b>0: Disable</b>; 1: Enable.For all + VR Indexes **/ - UINT8 Reserved30[5]; + UINT8 Irms[5]; /** Offset 0x06C7 - AvxDisable Enable or Disable AVX Support. This only applicable when all small core is disabled. @@ -1619,7 +1621,7 @@ typedef struct { /** Offset 0x06C9 - Reserved **/ - UINT8 Reserved31; + UINT8 Reserved30; /** Offset 0x06CA - CPU VR Power Delivery Design Used to communicate the power delivery design capability of the board. This value @@ -1630,7 +1632,7 @@ typedef struct { /** Offset 0x06CB - Reserved **/ - UINT8 Reserved32[32]; + UINT8 Reserved31[32]; /** Offset 0x06EB - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. @@ -1824,7 +1826,7 @@ typedef struct { /** Offset 0x0894 - Reserved **/ - UINT8 Reserved33; + UINT8 Reserved32; /** Offset 0x0895 - Touch Host Controller Port 1 Assignment Assign THC Port 1 @@ -1834,7 +1836,7 @@ typedef struct { /** Offset 0x0896 - Reserved **/ - UINT8 Reserved34[2]; + UINT8 Reserved33[2]; /** Offset 0x0898 - Touch Host Controller Port 1 Interrupt Pin Mux Set THC Port 1 Pin Muxing Value if signal can be enabled on multiple pads. Refer @@ -1844,7 +1846,7 @@ typedef struct { /** Offset 0x089C - Reserved **/ - UINT8 Reserved35; + UINT8 Reserved34; /** Offset 0x089D - PCIE RP Pcie Speed Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; @@ -1876,7 +1878,7 @@ typedef struct { /** Offset 0x0929 - Reserved **/ - UINT8 Reserved36[28]; + UINT8 Reserved35[28]; /** Offset 0x0945 - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism. @@ -1934,7 +1936,7 @@ typedef struct { /** Offset 0x09A1 - Reserved **/ - UINT8 Reserved37[3]; + UINT8 Reserved36[3]; /** Offset 0x09A4 - PCIe EQ phase 1 downstream transmitter port preset Allows to select the downstream port preset value that will be used during phase @@ -2223,7 +2225,7 @@ typedef struct { /** Offset 0x0A45 - Reserved **/ - UINT8 Reserved38; + UINT8 Reserved37; /** Offset 0x0A46 - Thermal Throttling Custimized T0Level Value Custimized T0Level value. @@ -2398,7 +2400,7 @@ typedef struct { /** Offset 0x0A6B - Reserved **/ - UINT8 Reserved39; + UINT8 Reserved38; /** Offset 0x0A6C - Thermal Device Temperature Decides the temperature. @@ -2423,7 +2425,7 @@ typedef struct { /** Offset 0x0A89 - Reserved **/ - UINT8 Reserved40[3]; + UINT8 Reserved39[3]; /** Offset 0x0A8C - xHCI High Idle Time LTR override Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting @@ -2473,7 +2475,7 @@ typedef struct { /** Offset 0x0A9C - Reserved **/ - UINT8 Reserved41[4]; + UINT8 Reserved40[4]; /** Offset 0x0AA0 - BgpdtHash[4] BgpdtHash values @@ -2487,7 +2489,7 @@ typedef struct { /** Offset 0x0AC4 - Reserved **/ - UINT8 Reserved42[4]; + UINT8 Reserved41[4]; /** Offset 0x0AC8 - BiosGuardModulePtr BiosGuardModulePtr default values @@ -2520,7 +2522,7 @@ typedef struct { /** Offset 0x0ADB - Reserved **/ - UINT8 Reserved43; + UINT8 Reserved42; /** Offset 0x0ADC - Change Default SVID Change the default SVID used in FSP to programming internal devices. This is only @@ -2620,7 +2622,7 @@ typedef struct { /** Offset 0x0B00 - Reserved **/ - UINT8 Reserved44[12]; + UINT8 Reserved43[12]; /** Offset 0x0B0C - PCIE Eq Ph3 Lane Param Cm CPU_PCIE_EQ_LANE_PARAM. Coefficient C-1. @@ -2713,7 +2715,7 @@ typedef struct { /** Offset 0x0BD1 - Reserved **/ - UINT8 Reserved45[3]; + UINT8 Reserved44[3]; /** Offset 0x0BD4 - CPU PCIE device override table pointer The PCIe device table is being used to override PCIe device ASPM settings. This @@ -2988,7 +2990,7 @@ typedef struct { /** Offset 0x0CA2 - Reserved **/ - UINT8 Reserved46[2]; + UINT8 Reserved45[2]; /** Offset 0x0CA4 - LogoPixelHeight Address Address of LogoPixelHeight @@ -3002,7 +3004,7 @@ typedef struct { /** Offset 0x0CAC - Reserved **/ - UINT8 Reserved47[5]; + UINT8 Reserved46[5]; /** Offset 0x0CB1 - RSR feature Enable or Disable RSR feature; 0: Disable; <b>1: Enable </b> @@ -3012,7 +3014,7 @@ typedef struct { /** Offset 0x0CB2 - Reserved **/ - UINT8 Reserved48[4]; + UINT8 Reserved47[4]; /** Offset 0x0CB6 - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b> @@ -3406,7 +3408,7 @@ typedef struct { /** Offset 0x0D2D - Reserved **/ - UINT8 Reserved49; + UINT8 Reserved48; /** Offset 0x0D2E - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments. @@ -3446,7 +3448,7 @@ typedef struct { /** Offset 0x0D3A - Reserved **/ - UINT8 Reserved50[2]; + UINT8 Reserved49[2]; /** Offset 0x0D3C - Package Long duration turbo mode power limit Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. @@ -3549,7 +3551,7 @@ typedef struct { /** Offset 0x0D73 - Reserved **/ - UINT8 Reserved51[4]; + UINT8 Reserved50[4]; /** Offset 0x0D77 - Intel Turbo Boost Max Technology 3.0 Intel Turbo Boost Max Technology 3.0. 0: Disabled; <b>1: Enabled</b> @@ -3621,7 +3623,7 @@ typedef struct { /** Offset 0x0D82 - Reserved **/ - UINT8 Reserved52; + UINT8 Reserved51; /** Offset 0x0D83 - Dual Tau Boost Enable, Disable Dual Tau Boost feature. This is only applicable for Desktop; <b>0: @@ -3632,7 +3634,7 @@ typedef struct { /** Offset 0x0D84 - Reserved **/ - UINT8 Reserved53[32]; + UINT8 Reserved52[32]; /** Offset 0x0DA4 - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): @@ -3681,7 +3683,7 @@ typedef struct { /** Offset 0x0DAB - Reserved **/ - UINT8 Reserved54; + UINT8 Reserved53; /** Offset 0x0DAC - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. @@ -3830,7 +3832,7 @@ typedef struct { /** Offset 0x0F96 - Reserved **/ - UINT8 Reserved55[16]; + UINT8 Reserved54[16]; /** Offset 0x0FA6 - FOMS Control Policy Choose the Foms Control Policy, <b>Default = 0 </b> @@ -3852,7 +3854,7 @@ typedef struct { /** Offset 0x0FAF - Reserved **/ - UINT8 Reserved56[33]; + UINT8 Reserved55[33]; /** Offset 0x0FD0 - FspEventHandler <b>Optional</b> pointer to the boot loader's implementation of FSP_EVENT_HANDLER. @@ -3867,7 +3869,7 @@ typedef struct { /** Offset 0x0FD5 - Reserved **/ - UINT8 Reserved57[11]; + UINT8 Reserved56[11]; } FSP_S_CONFIG; /** Fsp S UPD Configuration |