diff options
22 files changed, 14 insertions, 1801 deletions
diff --git a/Documentation/releases/coreboot-4.20-relnotes.md b/Documentation/releases/coreboot-4.20-relnotes.md index 2065f44ae7..ebaad659c9 100644 --- a/Documentation/releases/coreboot-4.20-relnotes.md +++ b/Documentation/releases/coreboot-4.20-relnotes.md @@ -40,6 +40,20 @@ noting, but not needing a full description. Plans to move platform support to a branch ------------------------------------------ +### Mainboard Scaleway Tagada + +According to the author of the mainboard scaleway/tagada, the mainboard +is not used anymore. Since the mainboard is not publicly available for +purchase and not used anywhere else, the usual deprecation process of 6 +months is not needed. + +Thus, to reduce the maintenance overhead for the community, support for +the following components will be removed from the master branch and will +be maintained on the release 4.19 branch. + + * Mainboard Scaleway Tagada + + ### Intel Quark SoC & Galileo mainboard The SoC Intel Quark is unmaintained and different efforts to revive it diff --git a/src/mainboard/scaleway/Kconfig b/src/mainboard/scaleway/Kconfig deleted file mode 100644 index 4635376d1e..0000000000 --- a/src/mainboard/scaleway/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if VENDOR_SCALEWAY - -choice - prompt "Mainboard model" - -source "src/mainboard/scaleway/*/Kconfig.name" - -endchoice - -source "src/mainboard/scaleway/*/Kconfig" - -config MAINBOARD_VENDOR - default "Scaleway" - -endif # VENDOR_SCALEWAY diff --git a/src/mainboard/scaleway/Kconfig.name b/src/mainboard/scaleway/Kconfig.name deleted file mode 100644 index abbc9e7132..0000000000 --- a/src/mainboard/scaleway/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config VENDOR_SCALEWAY - bool "Scaleway" diff --git a/src/mainboard/scaleway/tagada/Kconfig b/src/mainboard/scaleway/tagada/Kconfig deleted file mode 100644 index 1969fb0a12..0000000000 --- a/src/mainboard/scaleway/tagada/Kconfig +++ /dev/null @@ -1,25 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -if BOARD_SCALEWAY_TAGADA - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SOC_INTEL_DENVERTON_NS - select BOARD_ROMSIZE_KB_16384 - select HAVE_ACPI_TABLES - select CONSOLE_OVERRIDE_LOGLEVEL - select UART_OVERRIDE_BAUDRATE - -config MAINBOARD_DIR - default "scaleway/tagada" - -config MAINBOARD_PART_NUMBER - default "TAGADA" - -config BMC_INFO_LOC - hex "BMC information location in flash" - default 0xff802000 - help - Location of BMC SERIAL information. - -endif # BOARD_SCALEWAY_TAGADA diff --git a/src/mainboard/scaleway/tagada/Kconfig.name b/src/mainboard/scaleway/tagada/Kconfig.name deleted file mode 100644 index 67e5e0ae59..0000000000 --- a/src/mainboard/scaleway/tagada/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_SCALEWAY_TAGADA - bool "TAGADA" diff --git a/src/mainboard/scaleway/tagada/Makefile.inc b/src/mainboard/scaleway/tagada/Makefile.inc deleted file mode 100644 index 97bab195a4..0000000000 --- a/src/mainboard/scaleway/tagada/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -bootblock-y += bootblock.c - -romstage-y += hsio.c - -ramstage-y += ramstage.c -ramstage-y += hsio.c - -bootblock-y += bmcinfo.c -postcar-y += bmcinfo.c -romstage-y += bmcinfo.c -ramstage-y += bmcinfo.c -smm-y += bmcinfo.c - -CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/ diff --git a/src/mainboard/scaleway/tagada/acpi/mainboard.asl b/src/mainboard/scaleway/tagada/acpi/mainboard.asl deleted file mode 100644 index 160fbb7c5b..0000000000 --- a/src/mainboard/scaleway/tagada/acpi/mainboard.asl +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB) -{ - Device (PWRB) - { - Name(_HID, EisaId("PNP0C0C")) - - // Wake - Name(_PRW, Package(){0x1d, 0x05}) - } -} diff --git a/src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl b/src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl deleted file mode 100644 index 3482e23761..0000000000 --- a/src/mainboard/scaleway/tagada/acpi/mainboard_pci_irqs.asl +++ /dev/null @@ -1,173 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* This is board specific information: IRQ routing */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // [GREG]: Global Registers - Package() { 0x0004ffff, 0, 0, 16 }, - - // [RCEC]: Root Complex Event Collector - Package() { 0x0005ffff, 0, 0, 23 }, - - // [VRP2]: Virtual root port 2 - Package() { 0x0006ffff, 2, 0, 18 }, - - // [PEX0]: PCI Express Port 0 - Package() { 0x0009ffff, 0, 0, 16 }, - - // [PEX1]: PCI Express Port 1 - Package() { 0x000affff, 1, 0, 17 }, - - // [PEX2]: PCI Express Port 2 - Package() { 0x000bffff, 2, 0, 18 }, - - // [PEX3]: PCI Express Port 3 - Package() { 0x000cffff, 3, 0, 19 }, - - // [PEX4]: PCI Express Port 4 - Package() { 0x000effff, 0, 0, 20 }, - - // [PEX5]: PCI Express Port 5 - Package() { 0x000fffff, 1, 0, 21 }, - - // [PEX6]: PCI Express Port 6 - Package() { 0x0010ffff, 2, 0, 22 }, - - // [PEX7]: PCI Express Port 7 - Package() { 0x0011ffff, 3, 0, 23 }, - - // [SMB1]: SMBus controller - Package() { 0x0012ffff, 0, 0, 16 }, - - // [SAT0]: SATA controller 0 - Package() { 0x0013ffff, 0, 0, 20 }, - - // [SAT1]: SATA controller 1 - Package() { 0x0014ffff, 0, 0, 21 }, - - // [XHC0]: XHCI USB controller - Package() { 0x0015ffff, 0, 0, 19 }, - - // [VRP0]: Virtual root port 0 - Package() { 0x0016ffff, 0, 0, 16 }, - - // [VRP1]: Virtual root port 1 - Package() { 0x0017ffff, 1, 0, 17 }, - - // [HECI]: ME HECI - Package() { 0x0018ffff, 0, 0, 16 }, - - // [HEC2]: ME HECI2 - Package() { 0x0018ffff, 1, 0, 17 }, - - // [MEKT]: MEKT on PCH - Package() { 0x0018ffff, 2, 0, 18 }, - - // [HEC3]: ME HECI3 - Package() { 0x0018ffff, 3, 0, 19 }, - - // [UAR0]: UART 0 - Package() { 0x001affff, 0, 0, 16 }, - - // [UAR1]: UART 1 - Package() { 0x001affff, 1, 0, 17 }, - - // [UAR2]: UART 2 - Package() { 0x001affff, 2, 0, 18 }, - - // [EMMC]: eMMC - Package() { 0x001cffff, 0, 0, 16 }, - - // [P2SB]: Primary to sideband bridge - // [SMB0]: SMBus controller - // [NPK0]: Northpeak DFX - Package() { 0x001fffff, 0, 0, 23 }, - }) - } Else { - Return (Package() { - // [GREG]: Global Registers 0:4.0 - Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - - // [RCEC]: Root Complex Event Collector 0:5.0 - Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - - // [VRP2]: Virtual root port 2 0:6.0 - Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - - // [PEX0]: PCI Express Port 0 0:9.0 - Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - - // [PEX1]: PCI Express Port 1 0:a.0 - Package() { 0x000affff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - - // [PEX2]: PCI Express Port 2 0:b.0 - Package() { 0x000bffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - - // [PEX3]: PCI Express Port 3 0:c.0 - Package() { 0x000cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - - // [PEX4]: PCI Express Port 4 0:e.0 - Package() { 0x000effff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - - // [PEX5]: PCI Express Port 5 0:f.0 - Package() { 0x000fffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - - // [PEX6]: PCI Express Port 6 0:10.0 - Package() { 0x0010ffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, - - // [PEX7]: PCI Express Port 7 0:11.0 - Package() { 0x0011ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, - - // [SMB1]: SMBus controller 0:12.0 - Package() { 0x0012ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - - // [SAT0]: SATA controller 0 0:13.0 - Package() { 0x0013ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - - // [SAT1]: SATA controller 1 0:14.0 - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - - // [XHC0]: XHCI USB controller 0:15.0 - Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - - // [VRP0]: Virtual root port 0 0:16.0 - Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - - // [VRP1]: Virtual root port 1 0:17.0 - Package() { 0x0017ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - - // [HECI]: ME HECI 0:18.0 - Package() { 0x0018ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - - // [HEC2]: ME HECI2 0:18.1 - Package() { 0x0018ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - - // [MEKT]: MEKT on PCH 0:18.2 - Package() { 0x0018ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - - // [HEC3]: ME HECI3 0:18.3 - Package() { 0x0018ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - - // [UAR0]: UART 0 0:1a.0 - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - - // [UAR1]: UART 1 0:1a.1 - Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - - // [UAR2]: UART 2 0:1a.2 - Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - - // [EMMC]: eMMC 0:1c.0 - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - - // [P2SB]: Primary to sideband bridge - // [SMB0]: SMBus controller - // [NPK0]: Northpeak DFX - Package() { 0x001ffffF, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - }) - } -} diff --git a/src/mainboard/scaleway/tagada/acpi/platform.asl b/src/mainboard/scaleway/tagada/acpi/platform.asl deleted file mode 100644 index bbee0a2787..0000000000 --- a/src/mainboard/scaleway/tagada/acpi/platform.asl +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - Return(Package(){0,0}) -} diff --git a/src/mainboard/scaleway/tagada/acpi_tables.c b/src/mainboard/scaleway/tagada/acpi_tables.c deleted file mode 100644 index cfaffe32a8..0000000000 --- a/src/mainboard/scaleway/tagada/acpi_tables.c +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> -#include <acpi/acpi_gnvs.h> -#include <soc/nvs.h> - -void mainboard_fill_gnvs(struct global_nvs *gnvs) -{ - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - gnvs->s5u1 = 0; - - /* TPM Present */ - gnvs->tpmp = 0; -} - -void mainboard_fill_fadt(acpi_fadt_t *fadt) -{ - fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; -} diff --git a/src/mainboard/scaleway/tagada/bmcinfo.c b/src/mainboard/scaleway/tagada/bmcinfo.c deleted file mode 100644 index 2de2f2e3a0..0000000000 --- a/src/mainboard/scaleway/tagada/bmcinfo.c +++ /dev/null @@ -1,181 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <console/uart.h> -#include <types.h> - -#include "bmcinfo.h" - -typedef struct { - u32 magic0; // "BMCI" - u32 magic1; // "nfo0" - u16 length; - u16 chksum; - u8 uuid[16]; - u8 bmcSerial[9]; // as null terminated string - u8 slot; - u8 corebootVerbosityLevel; - u8 relaxSecurity; - u32 baudrate; - u8 bootOption; - u8 hwRev; // Note: Initial implementation ended here - u8 disableNic1; - u8 endMarker; // Insert new fields before -} biosBmcInfo_t; - -#define BIOSBMCINFO_MAGIC0 0x49434d42 -#define BIOSBMCINFO_MAGIC1 0x306f666e - -#define BMC_INFO ((biosBmcInfo_t *)CONFIG_BMC_INFO_LOC) - -enum biosBmcInfoValidFlag_e { - BMCINFO_UNTESTED = 0, - BMCINFO_INVALID, - BMCINFO_INVALID_WARNED, - BMCINFO_VALID_NEED_WARN, - BMCINFO_VALID, -}; -static bool bmcinfo_is_valid(size_t minsize) -{ - static enum biosBmcInfoValidFlag_e biosBmcInfoValidFlag; - const biosBmcInfo_t *bmc_info = BMC_INFO; - if (biosBmcInfoValidFlag == BMCINFO_UNTESTED) { - biosBmcInfoValidFlag = BMCINFO_INVALID; - if ((bmc_info->magic0 == BIOSBMCINFO_MAGIC0) - && (bmc_info->magic1 == BIOSBMCINFO_MAGIC1) - && (bmc_info->length >= offsetof(biosBmcInfo_t, hwRev)) - && (bmc_info->length <= 0x1000)) { - u16 chksum = 0 - (bmc_info->chksum & 0xff) - - (bmc_info->chksum >> 8); - int i; - for (i = 0; i < bmc_info->length ; i++) - chksum += ((u8 *)bmc_info)[i]; - if (bmc_info->chksum == chksum) { - if (bmc_info->length >= offsetof(biosBmcInfo_t, - endMarker)) - biosBmcInfoValidFlag = BMCINFO_VALID; - else - biosBmcInfoValidFlag = BMCINFO_VALID_NEED_WARN; - } - } - } - if (ENV_RAMSTAGE && biosBmcInfoValidFlag == BMCINFO_INVALID) { - int length = offsetof(biosBmcInfo_t, endMarker); - printk(BIOS_CRIT, "WARNING bmcInfo struct" - "is not available please update your BMC.\n"); - biosBmcInfoValidFlag = BMCINFO_INVALID_WARNED; - printk(BIOS_CRIT, "bmcInfo magic = \"%x-%x\"\n", - bmc_info->magic0, bmc_info->magic1); - printk(BIOS_CRIT, "bmcInfo length = %d expected = %d\"\n", - bmc_info->length, length); - u16 chksum = 0 - (bmc_info->chksum & 0xff) - - (bmc_info->chksum >> 8); - int i; - for (i = 0; i < bmc_info->length; i++) - chksum += ((u8 *)bmc_info)[i]; - printk(BIOS_CRIT, "bmcInfo chksum = 0x%x expected = 0x%x\"\n", - bmc_info->chksum, chksum); - } - if (ENV_RAMSTAGE && biosBmcInfoValidFlag == BMCINFO_VALID_NEED_WARN) { - printk(BIOS_CRIT, "WARNING bmcInfo struct" - " is incomplete please update your BMC.\n"); - - biosBmcInfoValidFlag = BMCINFO_VALID; - } - if (biosBmcInfoValidFlag < BMCINFO_VALID_NEED_WARN) - return false; - return (bmc_info->length >= minsize); -} - -#define IS_BMC_INFO_FIELD_VALID(field) \ - (bmcinfo_is_valid(offsetof(biosBmcInfo_t, field) \ - + sizeof(((biosBmcInfo_t *)0)->field))) - -char *bmcinfo_serial(void) -{ - if (IS_BMC_INFO_FIELD_VALID(bmcSerial)) - return (char *)BMC_INFO->bmcSerial; - return NULL; -} - -u8 *bmcinfo_uuid(void) -{ - if (IS_BMC_INFO_FIELD_VALID(uuid)) - return BMC_INFO->uuid; - return NULL; -} - -int bmcinfo_slot(void) -{ - if (IS_BMC_INFO_FIELD_VALID(slot)) - return BMC_INFO->slot; - return -1; -} - -int bmcinfo_hwrev(void) -{ - if (IS_BMC_INFO_FIELD_VALID(hwRev)) - return BMC_INFO->hwRev; - return -1; -} - -u32 bmcinfo_baudrate(void) -{ - if (IS_BMC_INFO_FIELD_VALID(baudrate)) - return BMC_INFO->baudrate; - return 0; -} - -int bmcinfo_coreboot_verbosity_level(void) -{ - if (IS_BMC_INFO_FIELD_VALID(corebootVerbosityLevel)) - return BMC_INFO->corebootVerbosityLevel & 0xf; - return BIOS_CRIT; -} - -int bmcinfo_fsp_verbosity_level(void) -{ - if (IS_BMC_INFO_FIELD_VALID(corebootVerbosityLevel)) - return BMC_INFO->corebootVerbosityLevel >> 4; - return 0; -} - -int bmcinfo_relax_security(void) -{ - if (IS_BMC_INFO_FIELD_VALID(relaxSecurity)) - return BMC_INFO->relaxSecurity; - return 0; -} - -int bmcinfo_boot_option(void) -{ - if (IS_BMC_INFO_FIELD_VALID(bootOption)) - return BMC_INFO->bootOption; - return 0; -} - -int bmcinfo_disable_nic1(void) -{ - if (IS_BMC_INFO_FIELD_VALID(disableNic1)) - return BMC_INFO->disableNic1; - return 0; -} - -/* Add override functions below */ - -/* Override default uart baudrate */ -unsigned int get_uart_baudrate(void) -{ - int baudrate = bmcinfo_baudrate(); - if (baudrate) - return baudrate; - return 115200; -} - -#if __CONSOLE_ENABLE__ -/* Override default console loglevel */ -int get_console_loglevel(void) -{ - return bmcinfo_coreboot_verbosity_level(); -} -#endif diff --git a/src/mainboard/scaleway/tagada/bmcinfo.h b/src/mainboard/scaleway/tagada/bmcinfo.h deleted file mode 100644 index 016de9b975..0000000000 --- a/src/mainboard/scaleway/tagada/bmcinfo.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef MAINBOARD_BMCINFO_H -#define MAINBOARD_BMCINFO_H - -// Do not place disks in boot order -#define BOOT_OPTION_NIC_ONLY 0 -// Boot to disk first (before network) -#define BOOT_OPTION_DISK_FIRST 1 -// Boot to disk second (after network) -#define BOOT_OPTION_DISK_SECOND 2 -// Boot order mask -#define BOOT_OPTION_ORDER_MASK 3 -// Reset after boot sequence (don't go to EFI shell) -#define BOOT_OPTION_NO_EFISHELL 0x80 - -char *bmcinfo_serial(void); -u8 *bmcinfo_uuid(void); -int bmcinfo_slot(void); -int bmcinfo_hwrev(void); -u32 bmcinfo_baudrate(void); -int bmcinfo_coreboot_verbosity_level(void); -int bmcinfo_fsp_verbosity_level(void); -int bmcinfo_relax_security(void); -int bmcinfo_boot_option(void); -int bmcinfo_disable_nic1(void); - -#endif /* MAINBOARD_BMCINFO_H */ diff --git a/src/mainboard/scaleway/tagada/board_info.txt b/src/mainboard/scaleway/tagada/board_info.txt deleted file mode 100644 index 2b94d46e86..0000000000 --- a/src/mainboard/scaleway/tagada/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Vendor name: Scaleway -Board name: Tagada -Category: server -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/scaleway/tagada/bootblock.c b/src/mainboard/scaleway/tagada/bootblock.c deleted file mode 100644 index a1c2c5d958..0000000000 --- a/src/mainboard/scaleway/tagada/bootblock.c +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootblock_common.h> -#include <console/console.h> -#include "bmcinfo.h" - -/* - * Display board serial early - */ - -void bootblock_mainboard_init(void) -{ - if (CONFIG(BOOTBLOCK_CONSOLE)) - printk(BIOS_SPEW, "Board Serial: %s.\n", bmcinfo_serial()); -} diff --git a/src/mainboard/scaleway/tagada/devicetree.cb b/src/mainboard/scaleway/tagada/devicetree.cb deleted file mode 100644 index 4de8bb5d80..0000000000 --- a/src/mainboard/scaleway/tagada/devicetree.cb +++ /dev/null @@ -1,60 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -chip soc/intel/denverton_ns - - # configure pirq routing - register "pirqa_routing" = "11" - register "pirqb_routing" = "10" - register "pirqc_routing" = "06" - register "pirqd_routing" = "07" - register "pirqe_routing" = "12" - register "pirqf_routing" = "14" - register "pirqg_routing" = "15" - register "pirqh_routing" = "15" - # configure device interrupt routing - register "ir00_routing" = "0x3217" # IR00, Dev31 - register "ir01_routing" = "0x3210" # IR01, Dev22 - register "ir02_routing" = "0x3211" # IR02, Dev23 - register "ir03_routing" = "0x3217" # IR03, Dev5 - register "ir04_routing" = "0x3212" # IR04, Dev6 - register "ir05_routing" = "0x3210" # IR05, Dev24 - register "ir06_routing" = "0x3214" # IR06, Dev19 - register "ir07_routing" = "0x3210" # IR07, Dev9/10/11/12 - register "ir08_routing" = "0x7654" # IR08, Dev14/15/16/17 - register "ir09_routing" = "0x3213" # IR09, Dev21 - register "ir10_routing" = "0x3210" # IR10, Dev26/18 - register "ir11_routing" = "0x3215" # IR11, Dev20 - register "ir12_routing" = "0x3210" # IR12, Dev27 - # configure interrupt polarity control - register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow - register "ipc1" = "0x00000000" # IPC1 - register "ipc2" = "0x00000000" # IPC2 - register "ipc3" = "0x00000000" # IPC3 - - device cpu_cluster 0 on end - - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 04.0 on end # RAS - device pci 05.0 on end # RCEC(Root Complex Event Collector) - device pci 06.0 on end # Virtual root port 2 (QAT) - device pci 09.0 on end # PCI Express Port 0, cluster #0, x4 - device pci 10.0 on end # PCI Express Port 6, cluster #1, x2 - device pci 11.0 on end # PCI Express Port 7, cluster #1, x2 - device pci 12.0 on end # SMBus Controller 1 - device pci 13.0 on end # SATA Controller 0 - device pci 14.0 on end # SATA Controller 1 - device pci 15.0 on end # XHCI USB Controller - device pci 16.0 on end # Virtual root port 0 (10GBE0) - device pci 17.0 on end # Virtual root port 1 (10GBE1) - device pci 18.0 on end # CSME HECI 1 - device pci 1a.0 on end # UART 0 - device pci 1a.1 off end # UART 1 - device pci 1a.2 off end # UART 2 - device pci 1c.0 on end # eMMC - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # PMC/ACPI - device pci 1f.4 on end # SMBus Controller 0 - device pci 1f.5 on end # SPI Controller - end -end diff --git a/src/mainboard/scaleway/tagada/dsdt.asl b/src/mainboard/scaleway/tagada/dsdt.asl deleted file mode 100644 index 3fa7422c46..0000000000 --- a/src/mainboard/scaleway/tagada/dsdt.asl +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> -DefinitionBlock( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 -) -{ - #include <acpi/dsdt_top.asl> - #include <southbridge/intel/common/acpi/platform.asl> - #include "acpi/platform.asl" - #include "acpi/mainboard.asl" - - // global NVS and variables - #include <soc/intel/denverton_ns/acpi/globalnvs.asl> - - #include <cpu/intel/common/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <soc/intel/denverton_ns/acpi/northcluster.asl> - #include <soc/intel/denverton_ns/acpi/southcluster.asl> - } - } - - #include <southbridge/intel/common/acpi/sleepstates.asl> -} diff --git a/src/mainboard/scaleway/tagada/gpio.h b/src/mainboard/scaleway/tagada/gpio.h deleted file mode 100644 index 28d1780e8e..0000000000 --- a/src/mainboard/scaleway/tagada/gpio.h +++ /dev/null @@ -1,320 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _MAINBOARD_GPIO_H -#define _MAINBOARD_GPIO_H - -#include <soc/gpio.h> - -#ifndef __ACPI__ - -#define PAD_NC_PWROK(pad, pull) PAD_CFG_GPI(pad, pull, PWROK) - -const struct pad_config tagada_gpio_config[] = { - // GBE0_SDP0 (GPIO_14) NC -/*ME PAD_CFG_NF(NORTH_ALL_GBE0_SDP0, NONE, PWROK, NF1), */ - // GBE1_SDP0 (GPIO_15) NC - PAD_CFG_NF(NORTH_ALL_GBE1_SDP0, NONE, PWROK, NF1), - // GBE2_I2C_CLK (GPIO_16) NC - PAD_CFG_GPO(NORTH_ALL_GBE0_SDP1, 0, PWROK), - // GBE2_I2C_DATA (GPIO_17) NC - PAD_NC_PWROK(NORTH_ALL_GBE1_SDP1, NONE), - // GBE2_SDP0 (GPIO_18) NC - PAD_CFG_NF(NORTH_ALL_GBE0_SDP2, NONE, PWROK, NF2), - // GBE3_SDP0 (GPIO_19) NC - PAD_CFG_NF(NORTH_ALL_GBE1_SDP2, NONE, PWROK, NF2), - // GBE3_I2C_CLK (GPIO_20) NC - PAD_CFG_GPO(NORTH_ALL_GBE0_SDP3, 0, PWROK), - // GBE3_I2C_DATA (GPIO_21) NC - PAD_NC_PWROK(NORTH_ALL_GBE1_SDP3, NONE), - // GBE2_LED0 (GPIO_22) Z1:NC / A0:ETH0_LED0 - PAD_CFG_NF(NORTH_ALL_GBE2_LED0, NONE, PWROK, NF1), - // GBE2_LED1 (GPIO_23) Z1:NC / A0:ETH0_LED1 - PAD_CFG_NF(NORTH_ALL_GBE2_LED1, NONE, PWROK, NF1), - // GBE0_I2C_CLK (GPIO_24) NC - PAD_CFG_GPO(NORTH_ALL_GBE0_I2C_CLK, 0, PWROK), - // GBE0_I2C_DATA (GPIO_25) NC - PAD_NC_PWROK(NORTH_ALL_GBE0_I2C_DATA, NONE), - // GBE1_I2C_CLK (GPIO_26) NC - PAD_CFG_GPO(NORTH_ALL_GBE1_I2C_CLK, 0, PWROK), - // GBE1_I2C_DATA (GPIO_27) NC - PAD_NC_PWROK(NORTH_ALL_GBE1_I2C_DATA, NONE), - // NCSI_RXD0 (GPIO_28) NC - PAD_CFG_NF(NORTH_ALL_NCSI_RXD0, NONE, PWROK, NF2), - // NCSI_CLK_IN (GPIO_29) Pull Down - PAD_CFG_NF(NORTH_ALL_NCSI_CLK_IN, NONE, PWROK, NF2), - // NCSI_RXD1 (GPIO_30) NC - PAD_CFG_NF(NORTH_ALL_NCSI_RXD1, NONE, PWROK, NF2), - // NCSI_CRS_DV (GPIO_31) NC - PAD_CFG_NF(NORTH_ALL_NCSI_CRS_DV, NONE, PWROK, NF2), - // NCSI_ARB_IN (GPIO_32) NC - PAD_CFG_NF(NORTH_ALL_NCSI_ARB_IN, NONE, PWROK, NF2), - // NCSI_TX_EN (GPIO_33) Pull Down - PAD_CFG_NF(NORTH_ALL_NCSI_TX_EN, NONE, PWROK, NF2), - // NCSI_TXD0 (GPIO_34) Pull Down - PAD_CFG_NF(NORTH_ALL_NCSI_TXD0, NONE, PWROK, NF2), - // NCSI_TXD1 (GPIO_35) Pull Down - PAD_CFG_NF(NORTH_ALL_NCSI_TXD1, NONE, PWROK, NF2), - // NCSI_ARB_OUT (GPIO_36) NC - PAD_CFG_NF(NORTH_ALL_NCSI_ARB_OUT, NONE, PWROK, NF2), - // GBE0_LED0 (GPIO_37) Z1:ETH0_LED0 / A1:ETH1_LED0 - PAD_CFG_NF(NORTH_ALL_GBE0_LED0, NONE, PWROK, NF1), - // GBE0_LED1 (GPIO_38) Z1:ETH0_LED1 / A1:ETH1_LED1 - PAD_CFG_NF(NORTH_ALL_GBE0_LED1, NONE, PWROK, NF1), - // GBE1_LED0 (GPIO_39) Z1:ETH1_LED0 / A1:NC - PAD_CFG_NF(NORTH_ALL_GBE1_LED0, NONE, PWROK, NF1), - // GBE1_LED1 (GPIO_40) Z1:ETH1_LED1 / A1:NC - PAD_CFG_NF(NORTH_ALL_GBE1_LED1, NONE, PWROK, NF1), - // ADR-COMPLETE (GPIO_0) LFFF: DVT_GPIO<0> : BOOTED, output - PAD_CFG_GPO(NORTH_ALL_GPIO_0, 0, PWROK), - // PCIE_CLKREQ0_N (GPIO_41) Pull Up - PAD_CFG_NF(NORTH_ALL_PCIE_CLKREQ0_N, NONE, PWROK, NF1), - // PCIE_CLKREQ1_N (GPIO_42) Pull Up - PAD_CFG_NF(NORTH_ALL_PCIE_CLKREQ1_N, NONE, PWROK, NF1), - // PCIE_CLKREQ2_N (GPIO_43) Pull Up - PAD_CFG_NF(NORTH_ALL_PCIE_CLKREQ2_N, NONE, PWROK, NF1), - // PCIE_CLKREQ3_N (GPIO_44) Pull Up - PAD_CFG_NF(NORTH_ALL_PCIE_CLKREQ3_N, NONE, PWROK, NF1), - // PCIE_CLKREQ4_N (GPIO_45) Pull Up - PAD_CFG_NF(NORTH_ALL_PCIE_CLKREQ4_N, NONE, PWROK, NF1), - // GBE_MDC (GPIO_1) NC - PAD_CFG_NF(NORTH_ALL_GPIO_1, NONE, PWROK, NF1), - // GBE_MDIO (GPIO_2) NC - PAD_CFG_NF(NORTH_ALL_GPIO_2, NONE, PWROK, NF1), - // SVID_ALERT_N (GPIO_47) SVID_ALERTn - PAD_CFG_NF(NORTH_ALL_SVID_ALERT_N, NONE, PWROK, NF1), - // SVID_DATA (GPIO_48) SVID_DATA - PAD_CFG_NF(NORTH_ALL_SVID_DATA, NONE, PWROK, NF1), - // SVID_CLK (GPIO_49) SVID_CLK - PAD_CFG_NF(NORTH_ALL_SVID_CLK, NONE, PWROK, NF1), - // THERMTRIP_N (GPIO_50) SOC_THERMTRIPn Pull Up - PAD_CFG_NF(NORTH_ALL_THERMTRIP_N, NONE, PWROK, NF1), - // PROCHOT_N (GPIO_51) PROCHOTn Pull Up - PAD_CFG_NF(NORTH_ALL_PROCHOT_N, NONE, PWROK, NF1), - // MEMHOT_N (GPIO_52) SOC_MEMHOTn - PAD_CFG_NF(NORTH_ALL_MEMHOT_N, NONE, PWROK, NF1), - // DFX_PORT_CLK0 (GPIO_53) NC - PAD_CFG_NF(SOUTH_DFX_DFX_PORT_CLK0, NONE, PWROK, NF1), - // DFX_PORT_CLK1 (GPIO_54) NC - PAD_CFG_NF(SOUTH_DFX_DFX_PORT_CLK1, NONE, PWROK, NF1), - // DFX_PORT0 (GPIO_55) NC - PAD_CFG_NF(SOUTH_DFX_DFX_PORT0, NONE, PWROK, NF1), - // DFX_PORT1 (GPIO_56) NC - PAD_CFG_NF(SOUTH_DFX_DFX_PORT1, NONE, PWROK, NF1), - // DFX_PORT2 (GPIO_57) NC - PAD_CFG_NF(SOUTH_DFX_DFX_PORT2, NONE, PWROK, NF1), - // DFX_PORT3 (GPIO_58) NC - PAD_CFG_NF(SOUTH_DFX_DFX_PORT3, NONE, PWROK, NF1), - // DFX_PORT4 (GPIO_59) NC - PAD_CFG_NF(SOUTH_DFX_DFX_PORT4, NONE, PWROK, NF1), - // DFX_PORT5 (GPIO_60) NC - PAD_CFG_NF(SOUTH_DFX_DFX_PORT5, NONE, PWROK, NF1), - // DFX_PORT6 (GPIO_61) NC - PAD_CFG_NF(SOUTH_DFX_DFX_PORT6, NONE, PWROK, NF1), - // DFX_PORT7 (GPIO_62) NC - PAD_CFG_NF(SOUTH_DFX_DFX_PORT7, NONE, PWROK, NF1), - // DFX_PORT8 (GPIO_63) NC - PAD_CFG_NF(SOUTH_DFX_DFX_PORT8, NONE, PWROK, NF1), - // DFX_PORT9 (GPIO_134) NC - PAD_CFG_NF(SOUTH_DFX_DFX_PORT9, NONE, PWROK, NF1), - // DFX_PORT10 (GPIO_135) NC - PAD_CFG_NF(SOUTH_DFX_DFX_PORT10, NONE, PWROK, NF1), - // DFX_PORT11 (GPIO_136) NC - PAD_CFG_NF(SOUTH_DFX_DFX_PORT11, NONE, PWROK, NF1), - // DFX_PORT12 (GPIO_137) NC - PAD_CFG_NF(SOUTH_DFX_DFX_PORT12, NONE, PWROK, NF1), - // DFX_PORT13 (GPIO_138) NC - PAD_CFG_NF(SOUTH_DFX_DFX_PORT13, NONE, PWROK, NF1), - // DFX_PORT14 (GPIO_139) NC - PAD_CFG_NF(SOUTH_DFX_DFX_PORT14, NONE, PWROK, NF1), - // DFX_PORT15 (GPIO_140) NC - PAD_CFG_NF(SOUTH_DFX_DFX_PORT15, NONE, PWROK, NF1), - // SPI_TPM_CS_N (GPIO_12) HS_TCO_WDT NC (Possible Pull Up) - PAD_CFG_NF(SOUTH_GROUP0_GPIO_12, NONE, PWROK, NF1), - // SMB5_GBE_ALRT_N (GPIO_13) LAN_ALRTn Pull Up - PAD_CFG_NF(SOUTH_GROUP0_SMB5_GBE_ALRT_N, NONE, PWROK, NF3), - // PCIE_CLKREQ5_N (GPIO_98) Pull Up - PAD_CFG_NF(SOUTH_GROUP0_PCIE_CLKREQ5_N, NONE, PWROK, NF1), - // PCIE_CLKREQ6_N (GPIO_99) Pull Up - PAD_CFG_NF(SOUTH_GROUP0_PCIE_CLKREQ6_N, NONE, PWROK, NF1), - // PCIE_CLKREQ7_N (GPIO_100) Pull Up - PAD_CFG_NF(SOUTH_GROUP0_PCIE_CLKREQ7_N, NONE, PWROK, NF1), - // UART0_RXD (GPIO_101) CONSOLE_RX - PAD_CFG_NF(SOUTH_GROUP0_UART0_RXD, NONE, PWROK, NF1), - // UART0_TXD (GPIO_102) CONSOLE_TX - PAD_CFG_NF(SOUTH_GROUP0_UART0_TXD, NONE, PWROK, NF1), - // SMB5_GBE_CLK (GPIO_103) LAN_SLC Pull Up - PAD_CFG_NF(SOUTH_GROUP0_SMB5_GBE_CLK, NONE, PWROK, NF3), - // SMB_GBE_DATA (GPIO_104) LAN_SDA Pull UP - PAD_CFG_NF(SOUTH_GROUP0_SMB5_GBE_DATA, NONE, PWROK, NF3), - // ERROR2_N (GPIO_105) ERRORn2 - PAD_CFG_NF(SOUTH_GROUP0_ERROR2_N, NONE, PWROK, NF1), - // ERROR1_N (GPIO_106) ERRORn1 - PAD_CFG_NF(SOUTH_GROUP0_ERROR1_N, NONE, PWROK, NF1), - // ERROR0_N (GPIO_107) ERRORn0 Pull Up - PAD_CFG_NF(SOUTH_GROUP0_ERROR0_N, NONE, PWROK, NF1), - // IERR_N (CATERR_N) (GPIO_108) IERRn (HardStrap Pull Up) - PAD_CFG_NF(SOUTH_GROUP0_IERR_N, NONE, PWROK, NF1), - // MCERR_N (GPIO_109) MCERR - PAD_CFG_NF(SOUTH_GROUP0_MCERR_N, NONE, PWROK, NF1), - // SMB0_LEG_CLK (GPIO_110) LEG_SCL Pull Up - PAD_CFG_NF(SOUTH_GROUP0_SMB0_LEG_CLK, NONE, PWROK, NF1), - // SMB0_LEG_DATA (GPIO_111) LEG_SDA Pull Up - PAD_CFG_NF(SOUTH_GROUP0_SMB0_LEG_DATA, NONE, PWROK, NF1), - // SMB0_LEG_ALRT_N (GPIO_112) Pull Up - PAD_CFG_NF(SOUTH_GROUP0_SMB0_LEG_ALRT_N, NONE, PWROK, NF1), - // SMB1_HOST_DATA (GPIO_113) HOST_SDA Pull Up -/*ME PAD_CFG_NF(SOUTH_GROUP0_SMB1_HOST_DATA, NONE, PWROK, NF1), */ - // SMB1_HOST_CLK (GPIO_114) HOST_SCL Pull Up -/*ME PAD_CFG_NF(SOUTH_GROUP0_SMB1_HOST_CLK, NONE, PWROK, NF1), */ - // SMB2_PECI_DATA (GPIO_115) Pull Up - PAD_CFG_NF(SOUTH_GROUP0_SMB2_PECI_DATA, NONE, PWROK, NF1), - // SMB2_PECI_CLK (GPIO_116) Pull Up - PAD_CFG_NF(SOUTH_GROUP0_SMB2_PECI_CLK, NONE, PWROK, NF1), - // SMB4_CSME0_DATA (GPIO_117) ME_SDA Pull Up -/*ME PAD_CFG_NF(SOUTH_GROUP0_SMB4_CSME0_DATA, NONE, PWROK, NF1), */ - // SMB4_CSME0_CLK (GPIO_118) ME_SCL Pull Up -/*ME PAD_CFG_NF(SOUTH_GROUP0_SMB4_CSME0_CLK, NONE, PWROK, NF1), */ - // SMB4_CSME0_ALRT_N (GPIO_119) ME_ALRTn Pull Up - PAD_CFG_NF(SOUTH_GROUP0_SMB4_CSME0_ALRT_N, NONE, PWROK, NF1), - // USB_OC0_N (GPIO_120) Pull Up - PAD_CFG_NF(SOUTH_GROUP0_USB_OC0_N, NONE, PWROK, NF1), - // FLEX_CLK_SE0 (GPIO_121) NC - PAD_CFG_NF(SOUTH_GROUP0_FLEX_CLK_SE0, NONE, PWROK, NF1), - // FLEX_CLK_SE1 (GPIO_122) NC - PAD_CFG_NF(SOUTH_GROUP0_FLEX_CLK_SE1, NONE, PWROK, NF1), - // GBE3_LED1 (GPIO_4) LFFF: M2A_CFGn : M2A_SATAn, input - PAD_CFG_GPI(SOUTH_GROUP0_GPIO_4, NONE, PWROK), - // SMB3_IE0_CLK (GPIO_5) LFFF: M2B_CFGn : M2B_SATAn, input - PAD_CFG_GPI(SOUTH_GROUP0_GPIO_5, NONE, PWROK), - // SMB3_IE0_DATA (GPIO_6) NC - PAD_CFG_NF(SOUTH_GROUP0_GPIO_6, NONE, PWROK, NF1), - // SMB3_IE0_ALERT_N (GPIO_7) NC - PAD_CFG_NF(SOUTH_GROUP0_GPIO_7, NONE, PWROK, NF1), - // SATA0_LED (GPIO_90) SATA_LED0 Pull Up - PAD_CFG_NF(SOUTH_GROUP0_SATA0_LED_N, NONE, PWROK, NF1), - // SATA1_LED (GPIO_91) SATA_LED1 Pull Up - PAD_CFG_NF(SOUTH_GROUP0_SATA1_LED_N, NONE, PWROK, NF1), - // SATA_PDETECT0 (GPIO_92) Pull Up - PAD_CFG_NF(SOUTH_GROUP0_SATA_PDETECT0, NONE, PWROK, NF2), - // SATA_PDETECT1 (GPIO_93) Pull Up - PAD_CFG_NF(SOUTH_GROUP0_SATA_PDETECT1, NONE, PWROK, NF2), - // UART1_RTS (GPIO_94) NC (Possible Pull Up) - PAD_CFG_NF(SOUTH_GROUP0_SATA0_SDOUT, NONE, PWROK, NF1), - // UART1_CTS (GPIO_95) NC (Possible Pull Up) - PAD_CFG_NF(SOUTH_GROUP0_SATA1_SDOUT, NONE, PWROK, NF1), - // UART1_RXD (GPIO_96) NC - PAD_CFG_NF(SOUTH_GROUP0_UART1_RXD, NONE, PWROK, NF1), - // UART1_TXD (GPIO_97) NC - PAD_CFG_NF(SOUTH_GROUP0_UART1_TXD, NONE, PWROK, NF1), - // SMB6_CSME1_DATA (GPIO_8) LFFF: DVT_GPIO<1> : Baud select, input - PAD_CFG_GPI(SOUTH_GROUP0_GPIO_8, NONE, PWROK), - // SMB6_CSME1_CLK (GPIO_9) LFFF: DVT_GPIO<2> : Verbose Traces, input - PAD_CFG_GPI(SOUTH_GROUP0_GPIO_9, NONE, PWROK), - // TCK (GPIO_141) n/a NC - PAD_CFG_NF(SOUTH_GROUP0_TCK, NONE, PWROK, NF1), - // TRST_N (GPIO_142) n/a NC - PAD_CFG_NF(SOUTH_GROUP0_TRST_N, NONE, PWROK, NF1), - // TMS (GPIO_143) n/a NC - PAD_CFG_NF(SOUTH_GROUP0_TMS, NONE, PWROK, NF1), - // TDI (GPIO_144) n/a NC - PAD_CFG_NF(SOUTH_GROUP0_TDI, NONE, PWROK, NF1), - // TDO (GPIO_145) n/a NC - PAD_CFG_NF(SOUTH_GROUP0_TDO, NONE, PWROK, NF1), - // CX_PRDY_N (GPIO_146) NC - PAD_CFG_NF(SOUTH_GROUP0_CX_PRDY_N, NONE, PWROK, NF1), - // CX-PREQ_N (GPIO_147) Pull Up - PAD_CFG_NF(SOUTH_GROUP0_CX_PREQ_N, NONE, PWROK, NF1), - // ME_RECVR_HDR (GPIO_148) ME_RECVR Pull Up -/*ME PAD_NC_PWROK(SOUTH_GROUP0_CTBTRIGINOUT, NONE), */ - // ADV_DBG_DFX_HDR (GPIO_149) NC - PAD_NC_PWROK(SOUTH_GROUP0_CTBTRIGOUT, NONE), - // LAD2_SPI_IRQ_N (GPIO_150) NC - PAD_NC_PWROK(SOUTH_GROUP0_DFX_SPARE2, NONE), - // SMB_PECI_ALRT_N (GPIO_151) Pull Up - PAD_NC_PWROK(SOUTH_GROUP0_DFX_SPARE3, NONE), - // SMB_CSME1_ALRT_N (GPIO_152) NC - PAD_NC_PWROK(SOUTH_GROUP0_DFX_SPARE4, NONE), - // SUSPWRDNACK (GPIO_79) SUSPWRDNACK Pull Up - PAD_CFG_NF(SOUTH_GROUP1_SUSPWRDNACK, NONE, PWROK, NF1), - // PMU_SUSCLK (GPIO_80) PMU_SUSCLK - PAD_CFG_NF(SOUTH_GROUP1_PMU_SUSCLK, NONE, PWROK, NF1), - // ADR_TRIGGER_N (GPIO_81) Pull Down - PAD_CFG_NF(SOUTH_GROUP1_ADR_TRIGGER, NONE, PWROK, NF1), - // PMU_SLP_S45_N (GPIO_82) SLP_S45n - PAD_CFG_NF(SOUTH_GROUP1_PMU_SLP_S45_N, NONE, PWROK, NF1), - // PMU_SLP_S3_N (GPIO_83) SLP_S3n - PAD_CFG_NF(SOUTH_GROUP1_PMU_SLP_S3_N, NONE, PWROK, NF1), - // PMU_WAKE_N (GPIO_84) PMU_WAKEn Pull Up - PAD_CFG_NF(SOUTH_GROUP1_PMU_WAKE_N, NONE, PWROK, NF1), - // PMU_PWRBTN_N (GPIO_85) PWNBTNn - PAD_CFG_NF(SOUTH_GROUP1_PMU_PWRBTN_N, NONE, PWROK, NF1), - // PMU_RESETBUTTON_N (GPIO_86) RSTBTNn - PAD_CFG_NF(SOUTH_GROUP1_PMU_RESETBUTTON_N, NONE, PWROK, NF1), - // PMU_PLTRST_N (GPIO_87) PLTRSTn - PAD_CFG_NF(SOUTH_GROUP1_PMU_PLTRST_N, NONE, PWROK, NF1), - // PMU_SUS_STAT_N (GPIO_88) SUS_STATn - PAD_CFG_NF(SOUTH_GROUP1_SUS_STAT_N, NONE, PWROK, NF1), - // TDB_CIO_PLUG_EVENT (GPIO_89) NC - PAD_NC_PWROK(SOUTH_GROUP1_SLP_S0IX_N, NONE), - // SPI_CS0_N (GPIO_72) SPI_CS0 - PAD_CFG_NF(SOUTH_GROUP1_SPI_CS0_N, NONE, PWROK, NF1), - // SPI_CS1_N (GPIO_73) NC - PAD_CFG_NF(SOUTH_GROUP1_SPI_CS1_N, NONE, PWROK, NF1), - // SPI_MOSI_IO0 (GPIO_74) SPI_MOSI - PAD_CFG_NF(SOUTH_GROUP1_SPI_MOSI_IO0, NONE, PWROK, NF1), - // SPI_MISO_IO1 (GPIO_75) SPI_MISO - PAD_CFG_NF(SOUTH_GROUP1_SPI_MISO_IO1, NONE, PWROK, NF1), - // SPI_IO2 (GPIO_76) NC - PAD_CFG_NF(SOUTH_GROUP1_SPI_IO2, NONE, PWROK, NF1), - // SPI_IO3 (GPIO_77) NC - PAD_CFG_NF(SOUTH_GROUP1_SPI_IO3, NONE, PWROK, NF1), - // SPI_CLK (GPIO_78) SPI_CLK - PAD_CFG_NF(SOUTH_GROUP1_SPI_CLK, NONE, PWROK, NF1), - // LPC_AD0 (GPIO_64) NC - PAD_CFG_NF(SOUTH_GROUP1_ESPI_IO0, NONE, PWROK, NF2), - // LPC_AD1 (GPIO_65) NC - PAD_CFG_NF(SOUTH_GROUP1_ESPI_IO1, NONE, PWROK, NF2), - // LPC_AD2 (GPIO_66) NC - PAD_CFG_NF(SOUTH_GROUP1_ESPI_IO2, NONE, PWROK, NF2), - // LPC_AD3 (GPIO_67) NC - PAD_CFG_NF(SOUTH_GROUP1_ESPI_IO3, NONE, PWROK, NF2), - // LPC_FRAME_N (GPIO_68) NC - PAD_CFG_NF(SOUTH_GROUP1_ESPI_CS0_N, NONE, PWROK, NF2), - // LPC_CLKOUT0 (GPIO_69) NC - PAD_CFG_NF(SOUTH_GROUP1_ESPI_CLK, NONE, PWROK, NF2), - // LPC_CLKOUT1 (GPIO_70) NC - PAD_CFG_NF(SOUTH_GROUP1_ESPI_RST_N, NONE, PWROK, NF2), - // LPC_CLKRUN_N (GPIO_71) Pull Up - PAD_CFG_NF(SOUTH_GROUP1_ESPI_ALRT0_N, NONE, PWROK, NF2), - // MFG_MODE_HDR (GPIO_10) MFG_MODE Pull Up - PAD_NC_PWROK(SOUTH_GROUP1_GPIO_10, NONE), - // LPC_SERIRQ (GPIO_11) NC - PAD_CFG_NF(SOUTH_GROUP1_GPIO_11, NONE, PWROK, NF2), - // EMMC-CMD (GPIO_123) NC - PAD_CFG_NF(SOUTH_GROUP1_EMMC_CMD, NONE, PWROK, NF1), - // EMMC-CSTROBE (GPIO_124) NC - PAD_CFG_NF(SOUTH_GROUP1_EMMC_STROBE, NONE, PWROK, NF1), - // EMMC-CLK (GPIO_125) NC - PAD_CFG_NF(SOUTH_GROUP1_EMMC_CLK, NONE, PWROK, NF1), - // EMMC-D0 (GPIO_126) NC - PAD_CFG_NF(SOUTH_GROUP1_EMMC_D0, NONE, PWROK, NF1), - // EMMC-D1 (GPIO_127) NC - PAD_CFG_NF(SOUTH_GROUP1_EMMC_D1, NONE, PWROK, NF1), - // EMMC-D2 (GPIO_128) NC - PAD_CFG_NF(SOUTH_GROUP1_EMMC_D2, NONE, PWROK, NF1), - // EMMC-D3 (GPIO_129) NC - PAD_CFG_NF(SOUTH_GROUP1_EMMC_D3, NONE, PWROK, NF1), - // EMMC-D4 (GPIO_130) NC - PAD_CFG_NF(SOUTH_GROUP1_EMMC_D4, NONE, PWROK, NF1), - // EMMC-D5 (GPIO_131) NC - PAD_CFG_NF(SOUTH_GROUP1_EMMC_D5, NONE, PWROK, NF1), - // EMMC-D6 (GPIO_132) NC - PAD_CFG_NF(SOUTH_GROUP1_EMMC_D6, NONE, PWROK, NF1), - // EMMC-D7 (GPIO_133) NC - PAD_CFG_NF(SOUTH_GROUP1_EMMC_D7, NONE, PWROK, NF1), - // IE_ROM GPIO (GPIO_3) HS_TSO NC (Possible Pull Up) - PAD_CFG_GPO(SOUTH_GROUP1_GPIO_3, 0, PWROK), -}; -#endif - -#endif /* _MAINBOARD_GPIO_H */ diff --git a/src/mainboard/scaleway/tagada/gpio_defs.h b/src/mainboard/scaleway/tagada/gpio_defs.h deleted file mode 100644 index b89ad5a8db..0000000000 --- a/src/mainboard/scaleway/tagada/gpio_defs.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _MAINBOARD_GPIO_DEFS_H -#define _MAINBOARD_GPIO_DEFS_H - -#include <soc/gpio_defs.h> - -// _GPIO_0 : LFFF: DVT_GPIO<0> : BOOTED -#define GPIO_GPIO_0 0 -#define R_PAD_CFG_DW0_GPIO_0 0x4d8 -#define PID_GPIO_0 PID_NorthCommunity - -// _GPIO_4 : LFFF: M2A_CFGn : M2A_SATAn -#define GPIO_GPIO_4 4 -#define R_PAD_CFG_DW0_GPIO_4 0x568 -#define PID_GPIO_4 PID_SouthCommunity - -// _GPIO_5 : LFFF: M2B_CFGn : M2B_SATAn -#define GPIO_GPIO_5 5 -#define R_PAD_CFG_DW0_GPIO_5 0x570 -#define PID_GPIO_5 PID_SouthCommunity - - -// _GPIO_8 : LFFF: DVT_GPIO<1> : Baud select -#define GPIO_GPIO_8 8 -#define R_PAD_CFG_DW0_GPIO_8 0x5c8 -#define PID_GPIO_8 PID_SouthCommunity - -// _GPIO_9 : LFFF: DVT_GPIO<2> : BIOS Verbose -#define GPIO_GPIO_9 9 -#define R_PAD_CFG_DW0_GPIO_9 0x5d0 -#define PID_GPIO_9 PID_SouthCommunity - -#endif /* _MAINBOARD_GPIO_DEFS_H */ diff --git a/src/mainboard/scaleway/tagada/hsio.c b/src/mainboard/scaleway/tagada/hsio.c deleted file mode 100644 index d6fb676ba0..0000000000 --- a/src/mainboard/scaleway/tagada/hsio.c +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <device/mmio.h> -#include <fast_spi_def.h> -#include <gpio_defs.h> -#include <hsio.h> -#include <soc/fiamux.h> -#include <string.h> - -#ifdef __RAMSTAGE__ -static void update_hsio_info_for_m2_slots(size_t num_of_entry, BL_HSIO_INFORMATION *config) -{ - uint32_t reg32; - bool m2a_pcie, m2b_pcie; - uint8_t entry; - BL_FIA_MUX_CONFIG_HOB *fiamux_hob_data = get_fiamux_hob_data(); - uint16_t supported_hsio_lanes; - void *spibar = fast_spi_get_bar(); - uint32_t hsfs; - - /* Configure FIA MUX PCD */ - supported_hsio_lanes = - (uint16_t)fiamux_hob_data->FiaMuxConfig.SkuNumLanesAllowed; - - /* Detects modules type */ - // _GPIO_4 : LFFF: M2A_CFGn : M2A_SATAn : 0 SATA, 1 PCIe - reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIO_4, R_PAD_CFG_DW0_GPIO_4)); - m2a_pcie = (reg32 & B_PCH_GPIO_RX_STATE) ? 1 : 0; - // _GPIO_5 : LFFF: M2A_CFGn : M2A_SATAn : 0 SATA, 1 PCIe - reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIO_5, R_PAD_CFG_DW0_GPIO_5)); - m2b_pcie = (reg32 & B_PCH_GPIO_RX_STATE) ? 1 : 0; - - printk(BIOS_DEBUG, - "GPIO values from M2 slots A:%d B:%d " - "(0=SATA, 1=PCIe or not populated)\n", - m2a_pcie, m2b_pcie); - - // HSIO default config is for PCIe, only update for SATA - // (also secondary PCIe lines are already set depending on SKU) - for (entry = 0; entry < num_of_entry; entry++) { - /* only update the active config */ - if (config[entry].NumLanesSupported != supported_hsio_lanes) - continue; - BL_ME_FIA_CONFIG *fia_config = &(config[entry].FiaConfig); - BL_ME_FIA_MUX_CONFIG *mux_config = - &(config[entry].FiaConfig.MuxConfiguration); - BL_ME_FIA_SATA_CONFIG *sata_config = - &(config[entry].FiaConfig.SataLaneConfiguration); - if (!m2a_pcie) { - // change Lane 14 config - mux_config->BL_MeFiaMuxLaneMuxSel.Lane14MuxSel = - BL_ME_FIA_MUX_LANE_SATA; - sata_config->BL_MeFiaSataLaneSataSel.Lane14SataSel = - BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED; - } - if (!m2b_pcie) { - // change Lane 12 config - mux_config->BL_MeFiaMuxLaneMuxSel.Lane12MuxSel = - BL_ME_FIA_MUX_LANE_SATA; - sata_config->BL_MeFiaSataLaneSataSel.Lane12SataSel = - BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED; - } - - /* Check SPIBAR for security override - at least one M2 slot is populated with SATA - the configuration is different form ME current one */ - hsfs = read32(spibar + SPIBAR_HSFSTS_CTL); - if ((!(hsfs & SPIBAR_HSFSTS_FDOPSS)) - && (!m2a_pcie || !m2b_pcie) - && memcmp(fia_config, - &fiamux_hob_data->FiaMuxConfig.FiaMuxConfig, - sizeof(BL_ME_FIA_CONFIG))) { - /* update configuration to NOT change ME config - as it will fail with security override set. */ - memcpy(fia_config, - &fiamux_hob_data->FiaMuxConfig.FiaMuxConfig, - sizeof(BL_ME_FIA_CONFIG)); - printk(BIOS_CRIT, "FLASH SECURITY OVERRIDE SET: " - "M2 SATA Slots are not available!\n"); - - } - } -} -#endif - -size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config) -{ - size_t num; - num = ARRAY_SIZE(tagada_hsio_config); -#ifdef __RAMSTAGE__ - update_hsio_info_for_m2_slots(num, tagada_hsio_config); -#endif - (*p_hsio_config) = (BL_HSIO_INFORMATION *)tagada_hsio_config; - return num; -} diff --git a/src/mainboard/scaleway/tagada/hsio.h b/src/mainboard/scaleway/tagada/hsio.h deleted file mode 100644 index 8a25a04011..0000000000 --- a/src/mainboard/scaleway/tagada/hsio.h +++ /dev/null @@ -1,616 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _MAINBOARD_HSIO_H -#define _MAINBOARD_HSIO_H - -#include <fsp/util.h> - -#ifndef __ACPI__ -DEVTREE_CONST BL_HSIO_INFORMATION tagada_hsio_config[] = { - /* - * Supported Lanes: - * 20 - * - * Bifurcation: - * PCIE cluster #0: x4x4 - * PCIE cluster #1: x2x2x2x2 (used for M2) - * - * FIA MUX config: - * Lane[00:03]-> disconnected - * Lane[08:11]-> 4 SATA side connectors - * Lane[12:15]-> 4 PCIe or 2 SATA (12,14) on M2 Connectors. - * M2 modules are detected; configuration updated by coreboot - * Lane[19]->USB3 rear I/O panel connector - */ - - /* SKU HSIO 20 (pcie [12-15] sata [8-11,12,14] USB [19]) */ - {BL_SKU_HSIO_20, - {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, - {/* ME_FIA_MUX_CONFIG */ - {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE15) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)}, - - /* ME_FIA_SATA_CONFIG */ - {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE04) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE05) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE06) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE07) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE08) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE09) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE10) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE11) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE12) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE13) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE14) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE15) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE16) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE17) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE18) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE19)}, - - /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */ - {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_0) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_1) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_2) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_3) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_4) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_5) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_6) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_7) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_0) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_1) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_2) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_3) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_4) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_5) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_6) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_7)} } }, - - /* SKU HSIO 12 (pcie [12-15] sata [8-11,12,14] USB [19]) */ - {BL_SKU_HSIO_12, - {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, - {/* ME_FIA_MUX_CONFIG */ - {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE15) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)}, - - /* ME_FIA_SATA_CONFIG */ - {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE04) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE05) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE06) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE07) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE08) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE09) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE10) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE11) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE12) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE13) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE14) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE15) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE16) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE17) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE18) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE19)}, - - /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */ - {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_0) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_1) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_2) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_3) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_4) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_5) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_6) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_7) | - - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_0) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_1) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_2) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_3) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_4) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_5) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_6) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_7)} } }, - - /* SKU HSIO 10 (pcie [12-15] sata [8-11,12,14] USB [19]) */ - {BL_SKU_HSIO_10, - {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, - {/* ME_FIA_MUX_CONFIG */ - {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE15) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)}, - - /* ME_FIA_SATA_CONFIG */ - {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE04) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE05) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE06) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE07) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE08) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE09) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE10) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE11) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE12) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE13) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE14) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE15) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE16) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE17) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE18) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE19)}, - - /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */ - {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_0) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_1) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_2) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_3) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_4) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_5) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_6) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_7) | - - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_0) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_1) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_2) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_3) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_4) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_5) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_6) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_7)} } }, - - /* SKU HSIO 8 (pcie [12-14] sata [8-11,12,14] USB [19]) */ - {BL_SKU_HSIO_08, - {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, - {/* ME_FIA_MUX_CONFIG */ - {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)}, - - /* ME_FIA_SATA_CONFIG */ - {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE04) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE05) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE06) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE07) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE08) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE09) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE10) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE11) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE12) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE13) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE14) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE15) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE16) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE17) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE18) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE19)}, - - /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */ - {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_0) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_1) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_2) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_3) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_4) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_5) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_6) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_7) | - - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_0) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_1) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_2) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_3) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_4) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_5) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_6) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_7)} } }, - - /* SKU HSIO 6 (pcie [12,14] sata [8-11,12,14] USB []) */ - {BL_SKU_HSIO_06, - {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, - {/* ME_FIA_MUX_CONFIG */ - {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE00) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE01) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE08) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE09) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE10) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE11) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE13) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE16) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) | - BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE19)}, - - /* ME_FIA_SATA_CONFIG */ - {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE04) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE05) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE06) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE07) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE08) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE09) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE10) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED, - BL_FIA_SATA_LANE11) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE12) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE13) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE14) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE15) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE16) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE17) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE18) | - BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED, - BL_FIA_SATA_LANE19)}, - - /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */ - {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_0) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_1) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_2) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_3) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_4) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_FIA_PCIE_ROOT_PORT_5) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_6) | - BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED, - BL_FIA_PCIE_ROOT_PORT_7) | - - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_0) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_1) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_2) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_3) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_4) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_5) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_6) | - BL_FIA_PCIE_ROOT_PORT_CONFIG( - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, - BL_FIA_PCIE_ROOT_PORT_7)} } } -}; -#endif -#endif /* _MAINBOARD_HSIO_H */ diff --git a/src/mainboard/scaleway/tagada/ramstage.c b/src/mainboard/scaleway/tagada/ramstage.c deleted file mode 100644 index bb0a385f7e..0000000000 --- a/src/mainboard/scaleway/tagada/ramstage.c +++ /dev/null @@ -1,87 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <string.h> -#include <fsp/api.h> -#include <soc/ramstage.h> -#include <smbios.h> -#include <spd.h> - -#include "bmcinfo.h" - -void mainboard_silicon_init_params(FSPS_UPD *params) -{ - /* Disable eMMC */ - params->FspsConfig.PcdEnableEmmc = 0; - - if (bmcinfo_disable_nic1()) - params->FspsConfig.PcdEnableGbE = 2; // disable lan 1 only -} - -/* Override smbios_mainboard_serial_number to retrieve it from BMC */ -const char *smbios_mainboard_serial_number(void) -{ - const char *bmc_serial = bmcinfo_serial(); - if (bmc_serial) - return bmc_serial; - return CONFIG_MAINBOARD_SERIAL_NUMBER; -} - -/* Override smbios_system_set_uuid */ -void smbios_system_set_uuid(u8 *uuid) -{ - const u8 *bmc_uuid = bmcinfo_uuid(); - if (bmc_uuid) - memcpy(uuid, bmc_uuid, 16); - /* leave all zero */ -} - -/* Override smbios_mainboard_version */ -const char *smbios_mainboard_version(void) -{ - const int hwRev = bmcinfo_hwrev(); - switch (hwRev) { - case 0: - return "Z0"; - case 1: - return "A0"; - case 2: - return "A1"; - } - return ""; -} - -/* Override smbios_mainboard_features_flags */ -u8 smbios_mainboard_feature_flags(void) -{ - return 0xc; -} - -/* Override smbios_mainboard_location_in_chassis */ -const char *smbios_mainboard_location_in_chassis(void) -{ - static char location[4] = "n/a"; - int slot = bmcinfo_slot(); - if (slot >= 0) - snprintf(location, 4, "N%d", slot); - return location; -} - -/* Override smbios_mainboard_board_type */ -smbios_board_type smbios_mainboard_board_type(void) -{ - return SMBIOS_BOARD_TYPE_SERVER_BLADE; -} - -smbios_enclosure_type smbios_mainboard_enclosure_type(void) -{ - return SMBIOS_ENCLOSURE_MULTI_SYSTEM_CHASSIS; -} - -/* Add any mainboard specific information for dimm */ -void mainboard_add_dimm_info( - struct memory_info *mem_info, - int channel, int dimm, int index) -{ - /* Mainboard only has DDR4 DIMM slots */ - mem_info->dimm[index].mod_type = DDR4_SPD_UDIMM; -} diff --git a/src/mainboard/scaleway/tagada/romstage.c b/src/mainboard/scaleway/tagada/romstage.c deleted file mode 100644 index e64356ef31..0000000000 --- a/src/mainboard/scaleway/tagada/romstage.c +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include "gpio.h" -#include <console/console.h> -#include <fsp/api.h> -#include <fsp/soc_binding.h> -#include "bmcinfo.h" - -void mainboard_config_gpios(void); -void mainboard_memory_init_params(FSPM_UPD *mupd); - -/* -* Configure GPIO depend on platform -*/ -void mainboard_config_gpios(void) -{ - size_t num; - const struct pad_config *table; - - printk(BIOS_SPEW, "Board Serial: %s.\n", bmcinfo_serial()); - /* Configure pads prior to SiliconInit() in case there's any - * dependencies during hardware initialization. - */ - table = tagada_gpio_config; - num = ARRAY_SIZE(tagada_gpio_config); - - if ((!table) || (!num)) { - printk(BIOS_ERR, "No valid GPIO table found!\n"); - return; - } - - printk(BIOS_INFO, "GPIO table: 0x%x, entry num: 0x%x!\n", - (uint32_t)table, (uint32_t)num); - gpio_configure_pads(table, num); -} - -void mainboard_memory_init_params(FSPM_UPD *mupd) -{ - mupd->FspmConfig.PcdFspDebugPrintErrorLevel = - bmcinfo_fsp_verbosity_level(); - - // Enable Rmt and Fast Boot by default, RMT will be run only on first - // boot or when dimms change - mupd->FspmConfig.PcdMrcRmtSupport = 1; - mupd->FspmConfig.PcdFastBoot = 1; -} |