diff options
| -rw-r--r-- | src/mainboard/amd/dinar/agesawrapper.c | 2 | ||||
| -rw-r--r-- | src/mainboard/amd/dinar/agesawrapper.h | 43 | ||||
| -rw-r--r-- | src/mainboard/amd/torpedo/agesawrapper.c | 2 | ||||
| -rw-r--r-- | src/mainboard/amd/torpedo/agesawrapper.h | 42 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb700/gpio_oem.h | 45 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb900/gpio_oem.h | 46 |
6 files changed, 95 insertions, 85 deletions
diff --git a/src/mainboard/amd/dinar/agesawrapper.c b/src/mainboard/amd/dinar/agesawrapper.c index 1338ee2096..f802bbef53 100644 --- a/src/mainboard/amd/dinar/agesawrapper.c +++ b/src/mainboard/amd/dinar/agesawrapper.c @@ -34,6 +34,8 @@ #include "Filecode.h" #include <arch/io.h> +#include <southbridge/amd/cimx/sb700/gpio_oem.h> + #define FILECODE UNASSIGNED_FILE_FILECODE /* ACPI table pointers returned by AmdInitLate */ diff --git a/src/mainboard/amd/dinar/agesawrapper.h b/src/mainboard/amd/dinar/agesawrapper.h index e4deb1b6ff..efce9c2af0 100644 --- a/src/mainboard/amd/dinar/agesawrapper.h +++ b/src/mainboard/amd/dinar/agesawrapper.h @@ -28,49 +28,6 @@ #define AMD_APU_SVID 0x1022 #define AMD_APU_SSID 0x1234 #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS -#define MMIO_NP_BIT BIT7 - -/* Hudson-2 ACPI PmIO Space Define */ -#define SB_ACPI_BASE_ADDRESS 0x0400 -#define ACPI_MMIO_BASE 0xFED80000 -#define SB_CFG_BASE 0x000 // DWORD -#define GPIO_BASE 0x100 // BYTE -#define SMI_BASE 0x200 // DWORD -#define PMIO_BASE 0x300 // DWORD -#define PMIO2_BASE 0x400 // BYTE -#define BIOS_RAM_BASE 0x500 // BYTE -#define CMOS_RAM_BASE 0x600 // BYTE -#define CMOS_BASE 0x700 // BYTE -#define ASF_BASE 0x900 // DWORD -#define SMBUS_BASE 0xA00 // DWORD -#define WATCHDOG_BASE 0xB00 // ?? -#define HPET_BASE 0xC00 // DWORD -#define IOMUX_BASE 0xD00 // BYTE -#define MISC_BASE 0xE00 -#define SERIAL_DEBUG_BASE 0x1000 -#define GFX_DAC_BASE 0x1400 -#define CEC_BASE 0x1800 -#define XHCI_BASE 0x1C00 -#define ACPI_SMI_DATA_PORT 0xB1 -#define R_SB_ACPI_PM1_STATUS 0x00 -#define R_SB_ACPI_PM1_ENABLE 0x02 -#define R_SB_ACPI_PM_CONTROL 0x04 -#define R_SB_ACPI_EVENT_STATUS 0x20 -#define R_SB_ACPI_EVENT_ENABLE 0x24 -#define B_PWR_BTN_STATUS BIT8 -#define B_WAKEUP_STATUS BIT15 -#define B_SCI_EN BIT0 -#define SB_PM_INDEX_PORT 0xCD6 -#define SB_PM_DATA_PORT 0xCD7 -#define SB_PMIOA_REG24 0x24 // AcpiMmioEn -#define MmioAddress( BaseAddr, Register ) \ - ( (UINTN)BaseAddr + \ - (UINTN)(Register) \ - ) -#define Mmio32Ptr( BaseAddr, Register ) \ - ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) ) -#define Mmio32( BaseAddr, Register ) \ - *Mmio32Ptr( BaseAddr, Register ) enum { PICK_DMI, /* DMI Interface */ diff --git a/src/mainboard/amd/torpedo/agesawrapper.c b/src/mainboard/amd/torpedo/agesawrapper.c index a379c677c0..9e1bbfd1f3 100644 --- a/src/mainboard/amd/torpedo/agesawrapper.c +++ b/src/mainboard/amd/torpedo/agesawrapper.c @@ -34,6 +34,8 @@ #include "Filecode.h" #include <arch/io.h> +#include <southbridge/amd/cimx/sb900/gpio_oem.h> + #define FILECODE UNASSIGNED_FILE_FILECODE /* ACPI table pointers returned by AmdInitLate */ diff --git a/src/mainboard/amd/torpedo/agesawrapper.h b/src/mainboard/amd/torpedo/agesawrapper.h index 5ca4cfad85..3a0aa0bb30 100644 --- a/src/mainboard/amd/torpedo/agesawrapper.h +++ b/src/mainboard/amd/torpedo/agesawrapper.h @@ -29,48 +29,6 @@ #define AMD_APU_SSID 0x1234 #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS -/* Hudson-2 ACPI PmIO Space Define */ -#define SB_ACPI_BASE_ADDRESS 0x0400 -#define ACPI_MMIO_BASE 0xFED80000 -#define SB_CFG_BASE 0x000 // DWORD -#define GPIO_BASE 0x100 // BYTE -#define SMI_BASE 0x200 // DWORD -#define PMIO_BASE 0x300 // DWORD -#define PMIO2_BASE 0x400 // BYTE -#define BIOS_RAM_BASE 0x500 // BYTE -#define CMOS_RAM_BASE 0x600 // BYTE -#define CMOS_BASE 0x700 // BYTE -#define ASF_BASE 0x900 // DWORD -#define SMBUS_BASE 0xA00 // DWORD -#define WATCHDOG_BASE 0xB00 // ?? -#define HPET_BASE 0xC00 // DWORD -#define IOMUX_BASE 0xD00 // BYTE -#define MISC_BASE 0xE00 -#define SERIAL_DEBUG_BASE 0x1000 -#define GFX_DAC_BASE 0x1400 -#define CEC_BASE 0x1800 -#define XHCI_BASE 0x1C00 -#define ACPI_SMI_DATA_PORT 0xB1 -#define R_SB_ACPI_PM1_STATUS 0x00 -#define R_SB_ACPI_PM1_ENABLE 0x02 -#define R_SB_ACPI_PM_CONTROL 0x04 -#define R_SB_ACPI_EVENT_STATUS 0x20 -#define R_SB_ACPI_EVENT_ENABLE 0x24 -#define B_PWR_BTN_STATUS BIT8 -#define B_WAKEUP_STATUS BIT15 -#define B_SCI_EN BIT0 -#define SB_PM_INDEX_PORT 0xCD6 -#define SB_PM_DATA_PORT 0xCD7 -#define SB_PMIOA_REG24 0x24 // AcpiMmioEn -#define MmioAddress( BaseAddr, Register ) \ - ( (UINTN)BaseAddr + \ - (UINTN)(Register) \ - ) -#define Mmio32Ptr( BaseAddr, Register ) \ - ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) ) -#define Mmio32( BaseAddr, Register ) \ - *Mmio32Ptr( BaseAddr, Register ) - enum { PICK_DMI, /* DMI Interface */ PICK_PSTATE, /* Acpi Pstate SSDT Table */ diff --git a/src/southbridge/amd/cimx/sb700/gpio_oem.h b/src/southbridge/amd/cimx/sb700/gpio_oem.h index bc05e2a5b9..7acd4f50b5 100644 --- a/src/southbridge/amd/cimx/sb700/gpio_oem.h +++ b/src/southbridge/amd/cimx/sb700/gpio_oem.h @@ -1,6 +1,51 @@ #ifndef _CIMX_SB_GPIO_OEM_H_ #define _CIMX_SB_GPIO_OEM_H_ +#define MMIO_NP_BIT BIT7 + +/* Hudson-2 ACPI PmIO Space Define */ +#define SB_ACPI_BASE_ADDRESS 0x0400 +#define ACPI_MMIO_BASE 0xFED80000 +#define SB_CFG_BASE 0x000 // DWORD +#define GPIO_BASE 0x100 // BYTE +#define SMI_BASE 0x200 // DWORD +#define PMIO_BASE 0x300 // DWORD +#define PMIO2_BASE 0x400 // BYTE +#define BIOS_RAM_BASE 0x500 // BYTE +#define CMOS_RAM_BASE 0x600 // BYTE +#define CMOS_BASE 0x700 // BYTE +#define ASF_BASE 0x900 // DWORD +#define SMBUS_BASE 0xA00 // DWORD +#define WATCHDOG_BASE 0xB00 // ?? +#define HPET_BASE 0xC00 // DWORD +#define IOMUX_BASE 0xD00 // BYTE +#define MISC_BASE 0xE00 +#define SERIAL_DEBUG_BASE 0x1000 +#define GFX_DAC_BASE 0x1400 +#define CEC_BASE 0x1800 +#define XHCI_BASE 0x1C00 +#define ACPI_SMI_DATA_PORT 0xB1 +#define R_SB_ACPI_PM1_STATUS 0x00 +#define R_SB_ACPI_PM1_ENABLE 0x02 +#define R_SB_ACPI_PM_CONTROL 0x04 +#define R_SB_ACPI_EVENT_STATUS 0x20 +#define R_SB_ACPI_EVENT_ENABLE 0x24 +#define B_PWR_BTN_STATUS BIT8 +#define B_WAKEUP_STATUS BIT15 +#define B_SCI_EN BIT0 +#define SB_PM_INDEX_PORT 0xCD6 +#define SB_PM_DATA_PORT 0xCD7 +#define SB_PMIOA_REG24 0x24 // AcpiMmioEn +#define MmioAddress( BaseAddr, Register ) \ + ( (UINTN)BaseAddr + \ + (UINTN)(Register) \ + ) +#define Mmio32Ptr( BaseAddr, Register ) \ + ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) ) +#define Mmio32( BaseAddr, Register ) \ + *Mmio32Ptr( BaseAddr, Register ) + + #define SB_GPIO_REG01 1 #define SB_GPIO_REG02 2 #define SB_GPIO_REG15 15 diff --git a/src/southbridge/amd/cimx/sb900/gpio_oem.h b/src/southbridge/amd/cimx/sb900/gpio_oem.h new file mode 100644 index 0000000000..7a61569992 --- /dev/null +++ b/src/southbridge/amd/cimx/sb900/gpio_oem.h @@ -0,0 +1,46 @@ +#ifndef _GPIO_OEM_H_ +#define _GPIO_OEM_H_ + +/* Hudson-2 ACPI PmIO Space Define */ +#define SB_ACPI_BASE_ADDRESS 0x0400 +#define ACPI_MMIO_BASE 0xFED80000 +#define SB_CFG_BASE 0x000 // DWORD +#define GPIO_BASE 0x100 // BYTE +#define SMI_BASE 0x200 // DWORD +#define PMIO_BASE 0x300 // DWORD +#define PMIO2_BASE 0x400 // BYTE +#define BIOS_RAM_BASE 0x500 // BYTE +#define CMOS_RAM_BASE 0x600 // BYTE +#define CMOS_BASE 0x700 // BYTE +#define ASF_BASE 0x900 // DWORD +#define SMBUS_BASE 0xA00 // DWORD +#define WATCHDOG_BASE 0xB00 // ?? +#define HPET_BASE 0xC00 // DWORD +#define IOMUX_BASE 0xD00 // BYTE +#define MISC_BASE 0xE00 +#define SERIAL_DEBUG_BASE 0x1000 +#define GFX_DAC_BASE 0x1400 +#define CEC_BASE 0x1800 +#define XHCI_BASE 0x1C00 +#define ACPI_SMI_DATA_PORT 0xB1 +#define R_SB_ACPI_PM1_STATUS 0x00 +#define R_SB_ACPI_PM1_ENABLE 0x02 +#define R_SB_ACPI_PM_CONTROL 0x04 +#define R_SB_ACPI_EVENT_STATUS 0x20 +#define R_SB_ACPI_EVENT_ENABLE 0x24 +#define B_PWR_BTN_STATUS BIT8 +#define B_WAKEUP_STATUS BIT15 +#define B_SCI_EN BIT0 +#define SB_PM_INDEX_PORT 0xCD6 +#define SB_PM_DATA_PORT 0xCD7 +#define SB_PMIOA_REG24 0x24 // AcpiMmioEn +#define MmioAddress( BaseAddr, Register ) \ + ( (UINTN)BaseAddr + \ + (UINTN)(Register) \ + ) +#define Mmio32Ptr( BaseAddr, Register ) \ + ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) ) +#define Mmio32( BaseAddr, Register ) \ + *Mmio32Ptr( BaseAddr, Register ) + +#endif |