diff options
4 files changed, 67 insertions, 22 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index 22a2b8d043..5f04e3643c 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -73,7 +73,14 @@ void enable_bios_reset_cpl(void); void enable_pam_region(void); /* API to enable Power Aware Interrupt Routing through MCHBAR */ void enable_power_aware_intr(void); - +/* API to get TOLUD base address */ +uint32_t sa_get_tolud_base(void); +/* API to get DSM size */ +size_t sa_get_dsm_size(void); +/* API to get GSM size */ +size_t sa_get_gsm_size(void); +/* API to get DPR size */ +size_t sa_get_dpr_size(void); /* * SoC overrides * diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 206f4a0f87..cb7af41518 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -100,26 +100,6 @@ static void sa_get_mem_map(struct device *dev, uint64_t *values) } /* - * Get DPR size incase CONFIG_SA_ENABLE_DPR is selected by SoC. - */ -static size_t get_dpr_size(void) -{ - uintptr_t dpr_reg; - size_t size = 0; - /* - * DMA Protected Range can be reserved below TSEG for PCODE patch - * or TXT/BootGuard related data. Rather than report a base address - * the DPR register reports the TOP of the region, which is the same - * as TSEG base. The region size is reported in MiB in bits 11:4. - */ - dpr_reg = pci_read_config32(SA_DEV_ROOT, DPR); - if (dpr_reg & DPR_EPM) - size = (dpr_reg & DPR_SIZE_MASK) << 16; - - return size; -} - -/* * These are the host memory ranges that should be added: * - 0 -> 0xa0000: cacheable * - 0xc0000 -> top_of_ram : cacheable @@ -159,7 +139,7 @@ static void sa_add_dram_resources(struct device *dev, int *resource_count) int index = *resource_count; if (IS_ENABLED(CONFIG_SA_ENABLE_DPR)) - dpr_size = get_dpr_size(); + dpr_size = sa_get_dpr_size(); top_of_ram = (uintptr_t)cbmem_top(); diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h index 29ce9ecd76..e0286922ed 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_def.h +++ b/src/soc/intel/common/block/systemagent/systemagent_def.h @@ -19,6 +19,12 @@ /* Device 0:0.0 PCI configuration space */ +/* GMCH Graphics Comntrol Register */ +#define GGC 0x50 +#define G_GMS_OFFSET 0x8 +#define G_GMS_MASK 0xff00 +#define G_GGMS_OFFSET 0x6 +#define G_GGMS_MASK 0xc0 /* DPR register incase CONFIG_SA_ENABLE_DPR is selected by SoC */ #define DPR 0x5c #define DPR_EPM (1 << 2) diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 7cf78e7352..855d953b68 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -132,3 +132,55 @@ void enable_bios_reset_cpl(void) bios_reset_cpl |= 3; MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; } + +uint32_t sa_get_tolud_base(void) +{ + /* All regions concerned for have 1 MiB alignment. */ + return ALIGN_DOWN(pci_read_config32(SA_DEV_ROOT, TOLUD), 1*MiB); +} + +static uint16_t sa_get_ggc_reg(void) +{ + return pci_read_config16(SA_DEV_ROOT, GGC); +} + +size_t sa_get_dsm_size(void) +{ + return (((sa_get_ggc_reg() & G_GMS_MASK) >> G_GMS_OFFSET) * 32*MiB); +} + +size_t sa_get_gsm_size(void) +{ + uint8_t ggms; + + ggms = (sa_get_ggc_reg() & G_GGMS_MASK) >> G_GGMS_OFFSET; + + /* + * Size of GSM: 0x0: No Preallocated Memory 0x1: 2MB Memory + * 0x2: 4MB Memory 0x3: 8MB Memory + */ + if (ggms) + return 1*MiB << ggms; + else + return 0; +} + +/* + * Get DPR size in case CONFIG_SA_ENABLE_DPR is selected by SoC. + */ +size_t sa_get_dpr_size(void) +{ + uintptr_t dpr_reg; + size_t size = 0; + /* + * DMA Protected Range can be reserved below TSEG for PCODE patch + * or TXT/BootGuard related data. Rather than report a base address + * the DPR register reports the TOP of the region, which is the same + * as TSEG base. The region size is reported in MiB in bits 11:4. + */ + dpr_reg = pci_read_config32(SA_DEV_ROOT, DPR); + if (dpr_reg & DPR_EPM) + size = (dpr_reg & DPR_SIZE_MASK) << 16; + + return size; +} |