diff options
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mct_d.c | 8 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mctardk4.c | 3 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mctcsi_d.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mctdqs_d.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mctsrc1p.c | 1 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mctsrc2p.c | 7 |
6 files changed, 1 insertions, 22 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index d3ae2a3cf4..62fc626e8a 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -1356,7 +1356,6 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, val |= dword; Set_NB32(dev, reg, val); } -// dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2)); print_tx("AutoCycTiming: Status ", pDCTstat->Status); print_tx("AutoCycTiming: ErrStatus ", pDCTstat->ErrStatus); @@ -1723,8 +1722,6 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, mct_EarlyArbEn_D(pMCTstat, pDCTstat); mctHookAfterAutoCfg(); -// dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2)); - print_tx("AutoConfig: Status ", pDCTstat->Status); print_tx("AutoConfig: ErrStatus ", pDCTstat->ErrStatus); print_tx("AutoConfig: ErrCode ", pDCTstat->ErrCode); @@ -1858,8 +1855,6 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat, reg = 0x80 + reg_off; /* Bank Addressing Register */ Set_NB32(dev, reg, BankAddrReg); -// dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2)); - print_tx("SPDSetBanks: Status ", pDCTstat->Status); print_tx("SPDSetBanks: ErrStatus ", pDCTstat->ErrStatus); print_tx("SPDSetBanks: ErrCode ", pDCTstat->ErrCode); @@ -2035,8 +2030,6 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat, mct_AfterStitchMemory(pMCTstat, pDCTstat, dct); } -// dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2)); - print_tx("StitchMemory: Status ", pDCTstat->Status); print_tx("StitchMemory: ErrStatus ", pDCTstat->ErrStatus); print_tx("StitchMemory: ErrCode ", pDCTstat->ErrCode); @@ -2399,7 +2392,6 @@ static u8 Get_DIMMAddress_D(struct DCTStatStruc *pDCTstat, u8 i) u8 *p; p = pDCTstat->DIMMAddr; - //mct_BeforeGetDIMMAddress(); return p[i]; } diff --git a/src/northbridge/amd/amdmct/mct/mctardk4.c b/src/northbridge/amd/amdmct/mct/mctardk4.c index 7e1d91af5c..8815943c72 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk4.c +++ b/src/northbridge/amd/amdmct/mct/mctardk4.c @@ -30,9 +30,6 @@ void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, &(pDCTstat->CH_ADDR_TMG[dct]), &(pDCTstat->CH_ODC_CTL[dct]), &pDCTstat->_2Tmode); -// print_tx("1 CH_ODC_CTL: ", pDCTstat->CH_ODC_CTL[dct]); -// print_tx("1 CH_ADDR_TMG: ", pDCTstat->CH_ADDR_TMG[dct]); - if (pDCTstat->MAdimms[dct] == 1) pDCTstat->CH_ODC_CTL[dct] |= 0x20000000; /* 75ohms */ else diff --git a/src/northbridge/amd/amdmct/mct/mctcsi_d.c b/src/northbridge/amd/amdmct/mct/mctcsi_d.c index 4841b73bb0..1c86239cfc 100644 --- a/src/northbridge/amd/amdmct/mct/mctcsi_d.c +++ b/src/northbridge/amd/amdmct/mct/mctcsi_d.c @@ -132,8 +132,6 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, print_t("InterleaveBanks_D: Banks Interleaved "); } /* DoIntlv */ -// dump_pci_device(PCI_DEV(0, 0x18+pDCTstat->Node_ID, 2)); - print_tx("InterleaveBanks_D: Status ", pDCTstat->Status); print_tx("InterleaveBanks_D: ErrStatus ", pDCTstat->ErrStatus); print_tx("InterleaveBanks_D: ErrCode ", pDCTstat->ErrCode); diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index e0c7761011..63631623cf 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -437,8 +437,6 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat, u8 dqsDelay_end; u8 tmp, valid; -// print_tx("TrainDQSPos: Node_ID", pDCTstat->Node_ID); -// print_tx("TrainDQSPos: Direction", pDCTstat->Direction); /* MutualCSPassW: each byte represents a bitmap of pass/fail per * ByteLane. The indext within MutualCSPassW is the delay value diff --git a/src/northbridge/amd/amdmct/mct/mctsrc1p.c b/src/northbridge/amd/amdmct/mct/mctsrc1p.c index c1b1133925..bfd103b311 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc1p.c @@ -61,7 +61,6 @@ static u8 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel, p[i] = val; } -// pDCTstat->DimmTrainFail &= ~(1<<Receiver+Channel); return MaxValue; } diff --git a/src/northbridge/amd/amdmct/mct/mctsrc2p.c b/src/northbridge/amd/amdmct/mct/mctsrc2p.c index c7c92acb17..7454f5390a 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc2p.c @@ -60,12 +60,9 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, u8 *p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; u8 bn; bn = 8; -// print_tx("mct_Get_Start_RcvrEnDly_Pass: Channel:", Channel); -// print_tx("mct_Get_Start_RcvrEnDly_Pass: Receiver:", Receiver); + for (i = 0; i < bn; i++) { val = p[i]; -// print_tx("mct_Get_Start_RcvrEnDly_Pass: i:", i); -// print_tx("mct_Get_Start_RcvrEnDly_Pass: val:", val); if (val > max) { max = val; } @@ -123,9 +120,7 @@ u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, for (i = 0; i < bn; i++) { val = p[i]; /* Add 1/2 Memlock delay */ - //val += Pass1MemClkDly; val += 0x5; // NOTE: middle value with DQSRCVEN_SAVED_GOOD_TIMES - //val += 0x02; p[i] = val; pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel)); } |