diff options
| -rw-r--r-- | src/drivers/gic/Kconfig | 4 | ||||
| -rw-r--r-- | src/drivers/gic/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/drivers/gic/gic.c | 148 | ||||
| -rw-r--r-- | src/drivers/gic/gic.h | 61 | ||||
| -rw-r--r-- | src/include/gic.h | 26 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/gic.c | 14 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/ramstage.c | 4 |
9 files changed, 0 insertions, 260 deletions
diff --git a/src/drivers/gic/Kconfig b/src/drivers/gic/Kconfig deleted file mode 100644 index 193311fc05..0000000000 --- a/src/drivers/gic/Kconfig +++ /dev/null @@ -1,4 +0,0 @@ -config GIC - def_bool n - help - This option enables GIC support, the ARM generic interrupt controller. diff --git a/src/drivers/gic/Makefile.inc b/src/drivers/gic/Makefile.inc deleted file mode 100644 index 51e3e199e2..0000000000 --- a/src/drivers/gic/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-$(CONFIG_GIC) += gic.c diff --git a/src/drivers/gic/gic.c b/src/drivers/gic/gic.c deleted file mode 100644 index 610c0b8e89..0000000000 --- a/src/drivers/gic/gic.c +++ /dev/null @@ -1,148 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/cpu.h> -#include <device/mmio.h> -#include <console/console.h> -#include <gic.h> -#include <stddef.h> -#include "gic.h" - -enum { - ENABLE_GRP0 = 0x1 << 0, - ENABLE_GRP1 = 0x1 << 1, - FIQ_BYP_DIS_GRP0 = 0x1 << 5, - IRQ_BYP_DIS_GRP0 = 0x1 << 6, - FIQ_BYP_DIS_GRP1 = 0x1 << 7, - IRQ_BYP_DIS_GRP1 = 0x1 << 8, -}; - -struct gic { - struct gicd_mmio *gicd; - struct gicc_mmio *gicc; - size_t num_interrupts; - unsigned int version; - unsigned int security_extensions; -}; - -static struct gic *gic_get(void) -{ - static struct gic gic; - - if (gic.gicd == NULL) { - uint32_t typer; - - gic.gicd = gicd_base(); - gic.gicc = gicc_base(); - typer = read32(&gic.gicd->typer); - gic.num_interrupts = 32 * ((typer & 0x1f) + 1); - gic.security_extensions = !!(typer & (1 << 10)); - gic.version = (read32(&gic.gicd->icpidr2) & 0xf0) >> 4; - - printk(BIOS_DEBUG, "GICv%d - %zu ints %s GICD=%p GICC=%p\n", - gic.version, gic.num_interrupts, - gic.security_extensions ? "SecExtn" : "", - gic.gicd, gic.gicc); - } - - return &gic; -} - -static inline uint32_t gic_read(uint32_t *base) -{ - return read32(base); -} - -static inline void gic_write(uint32_t *base, uint32_t val) -{ - write32(base, val); -} - -static void gic_write_regs(uint32_t *base, size_t num_regs, uint32_t val) -{ - size_t i; - - for (i = 0; i < num_regs; i++) - gic_write(base++, val); -} - -static void gic_write_banked_regs(uint32_t *base, size_t interrupts_per_reg, - uint32_t val) -{ - /* 1st 32 interrupts are banked per CPU. */ - gic_write_regs(base, 32 / interrupts_per_reg, val); -} - -void gic_init(void) -{ - struct gic *gic; - struct gicd_mmio *gicd; - struct gicc_mmio *gicc; - uint32_t cpu_mask; - - gic = gic_get(); - gicd = gic->gicd; - gicc = gic->gicc; - - /* Enable Group 0 and Group 1 in GICD -- banked regs. */ - gic_write(&gicd->ctlr, ENABLE_GRP0 | ENABLE_GRP1); - - /* Enable Group 0 and Group 1 in GICC and enable all priroity levels. */ - gic_write(&gicc->ctlr, ENABLE_GRP0 | ENABLE_GRP1); - gic_write(&gicc->pmr, 1 << 7); - - cpu_mask = 1 << smp_processor_id(); - cpu_mask |= cpu_mask << 8; - cpu_mask |= cpu_mask << 16; - - /* Only write banked registers for secondary CPUs. */ - if (smp_processor_id()) { - gic_write_banked_regs(&gicd->itargetsr[0], 4, cpu_mask); - /* Put interrupts into Group 1. */ - gic_write_banked_regs(&gicd->igroupr[0], 32, ~0x0); - /* Allow Non-secure access to everything. */ - gic_write_banked_regs(&gicd->nsacr[0], 16, ~0x0); - return; - } - - /* All interrupts routed to processors that execute this function. */ - gic_write_regs(&gicd->itargetsr[0], gic->num_interrupts / 4, cpu_mask); - /* Put all interrupts into Gropup 1. */ - gic_write_regs(&gicd->igroupr[0], gic->num_interrupts / 32, ~0x0); - /* Allow Non-secure access to everything. */ - gic_write_regs(&gicd->nsacr[0], gic->num_interrupts / 16, ~0x0); -} - -void gic_disable(void) -{ - struct gic *gic; - struct gicc_mmio *gicc; - - gic = gic_get(); - gicc = gic->gicc; - - /* Disable secure, non-secure interrupts. */ - uint32_t val = gic_read(&gicc->ctlr); - val &= ~(ENABLE_GRP0 | ENABLE_GRP1); - /* - * Enable the IRQ/FIQ BypassDisable bits to bypass the IRQs. - * So the CPU can wake up from power gating state when the GIC - * was disabled. - */ - val |= FIQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP0 | - FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; - gic_write(&gicc->ctlr, val); -} - -void gic_enable(void) -{ - struct gic *gic; - struct gicc_mmio *gicc; - - gic = gic_get(); - gicc = gic->gicc; - - /* Enable secure, non-secure interrupts. */ - uint32_t val = gic_read(&gicc->ctlr); - val |= (ENABLE_GRP0 | ENABLE_GRP1); - gic_write(&gicc->ctlr, val); -} diff --git a/src/drivers/gic/gic.h b/src/drivers/gic/gic.h deleted file mode 100644 index 03fed63b49..0000000000 --- a/src/drivers/gic/gic.h +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef DRIVERS_GIC_H -#define DRIVERS_GIC_H - -#include <stdint.h> - -#define NR(start, end) (((end) - (start)) / sizeof(uint32_t)) - -struct gicd_mmio { - uint32_t ctlr; /* 0x000 - 0x003 */ - uint32_t typer; /* 0x004 - 0x007 */ - uint32_t iidr; /* 0x008 - 0x00b */ - uint32_t reserved_1[NR(0xc, 0x80)]; /* 0x00c - 0x07f */ - uint32_t igroupr[NR(0x80, 0x100)]; /* 0x080 - 0x0ff */ - uint32_t isenabler[NR(0x100, 0x180)]; /* 0x100 - 0x17f */ - uint32_t icenabler[NR(0x180, 0x200)]; /* 0x180 - 0x1ff */ - uint32_t ispendr[NR(0x200, 0x280)]; /* 0x200 - 0x27f */ - uint32_t icpendr[NR(0x280, 0x300)]; /* 0x280 - 0x2ff */ - uint32_t isactiver[NR(0x300, 0x380)]; /* 0x300 - 0x37f */ - uint32_t icactiver[NR(0x380, 0x400)]; /* 0x380 - 0x3ff */ - uint32_t ipriorityr[NR(0x400, 0x7fc)]; /* 0x400 - 0x7fb */ - uint32_t reserved_2[NR(0x7fc, 0x800)]; /* 0x7fc - 0x7ff */ - uint32_t itargetsr[NR(0x800, 0xbfc)]; /* 0x800 - 0xbfb */ - uint32_t reserved_3[NR(0xbfc, 0xc00)]; /* 0xbfc - 0x2ff */ - uint32_t icfgr[NR(0xc00, 0xd00)]; /* 0xc00 - 0xcff */ - uint32_t reserved_4[NR(0xd00, 0xe00)]; /* 0xd00 - 0xdff */ - uint32_t nsacr[NR(0xe00, 0xf00)]; /* 0xe00 - 0xeff */ - uint32_t sgir; /* 0xf00 - 0xf03 */ - uint32_t reserved_5[NR(0xf04, 0xf10)]; /* 0xf04 - 0xf0f */ - uint32_t cpendsgir[NR(0xf10, 0xf20)]; /* 0xf10 - 0xf1f */ - uint32_t spendsgir[NR(0xf20, 0xf30)]; /* 0xf20 - 0xf2f */ - uint32_t reserved_6[NR(0xf30, 0xfe8)]; /* 0xf30 - 0xfe7 */ - uint32_t icpidr2; /* 0xfe8 - 0xfeb */ - uint32_t reserved_7[NR(0xfec, 0x1000)]; /* 0xfec - 0xfff */ -}; - -struct gicc_mmio { - uint32_t ctlr; /* 0x000 - 0x003 */ - uint32_t pmr; /* 0x004 - 0x007 */ - uint32_t bpr; /* 0x008 - 0x00b */ - uint32_t iar; /* 0x00c - 0x00f */ - uint32_t eoir; /* 0x010 - 0x013 */ - uint32_t rpr; /* 0x014 - 0x017 */ - uint32_t hppir; /* 0x018 - 0x01b */ - uint32_t apbr; /* 0x01c - 0x01f */ - uint32_t aiar; /* 0x020 - 0x023 */ - uint32_t aeoir; /* 0x024 - 0x027 */ - uint32_t ahppir; /* 0x028 - 0x02b */ - uint32_t resered_1[NR(0x2c, 0xd0)]; /* 0x02c - 0x0cf */ - uint32_t apr[NR(0xd0, 0xe0)]; /* 0x0d0 - 0x0df */ - uint32_t nsapr[NR(0xe0, 0xf0)]; /* 0x0e0 - 0x0ef */ - uint32_t resered_2[NR(0xf0, 0xfc)]; /* 0x0f0 - 0x0fb */ - uint32_t iidr; /* 0x0fc - 0x0ff */ - uint32_t reserved_3[NR(0x100, 0x1000)]; /* 0x100 - 0xfff */ - uint32_t dir; /* 0x1000 - 0x1003 */ -}; - -#undef NR - -#endif /* DRIVERS_GIC_H */ diff --git a/src/include/gic.h b/src/include/gic.h deleted file mode 100644 index a4201bb440..0000000000 --- a/src/include/gic.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef GIC_H -#define GIC_H - -#if CONFIG(GIC) - -/* Initialize the GIC on the currently processor, including GICD and GICC. */ -void gic_init(void); -void gic_disable(void); -void gic_enable(void); - -/* Return a pointer to the base of the GIC distributor mmio region. */ -void *gicd_base(void); - -/* Return a pointer to the base of the GIC CPU mmio region. */ -void *gicc_base(void); - -#else /* CONFIG_GIC */ - -static inline void gic_init(void) {} -static inline void gic_disable(void) {} - -#endif /* CONFIG_GIC */ - -#endif /* GIC_H */ diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 32748f3b6b..4fcbaffbee 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -6,7 +6,6 @@ config SOC_NVIDIA_TEGRA210 select ARCH_VERSTAGE_ARMV4 select ARCH_ROMSTAGE_ARMV4 select ARCH_RAMSTAGE_ARMV8_64 - select GIC select HAVE_UART_SPECIAL select ARM64_USE_ARM_TRUSTED_FIRMWARE select GENERIC_GPIO_LIB diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc index e213751308..f76ab347e0 100644 --- a/src/soc/nvidia/tegra210/Makefile.inc +++ b/src/soc/nvidia/tegra210/Makefile.inc @@ -79,7 +79,6 @@ ramstage-y += i2c6.c ramstage-y += ape.c ramstage-y += power.c ramstage-y += dma.c -ramstage-y += gic.c ramstage-y += monotonic_timer.c ramstage-y += padconfig.c ramstage-y += funitcfg.c diff --git a/src/soc/nvidia/tegra210/gic.c b/src/soc/nvidia/tegra210/gic.c deleted file mode 100644 index f02ce53712..0000000000 --- a/src/soc/nvidia/tegra210/gic.c +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <gic.h> -#include <soc/addressmap.h> - -void *gicd_base(void) -{ - return (void *)(uintptr_t)TEGRA_GICD_BASE; -} - -void *gicc_base(void) -{ - return (void *)(uintptr_t)TEGRA_GICC_BASE; -} diff --git a/src/soc/nvidia/tegra210/ramstage.c b/src/soc/nvidia/tegra210/ramstage.c index c470e6b5cd..50249b7051 100644 --- a/src/soc/nvidia/tegra210/ramstage.c +++ b/src/soc/nvidia/tegra210/ramstage.c @@ -5,7 +5,6 @@ #include <cbmem.h> #include <console/console.h> #include <device/mmio.h> -#include <gic.h> #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/mmu_operations.h> @@ -41,9 +40,6 @@ static void mselect_enable_wrap(void) void ramstage_entry(void); void ramstage_entry(void) { - /* TODO: Is this still needed? */ - gic_init(); - /* TODO: Move arch timer setup to BL31? */ arm64_arch_timer_init(); |