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-rw-r--r--src/soc/intel/alderlake/Kconfig1
-rw-r--r--src/soc/intel/alderlake/romstage/fsp_params.c3
2 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 0c68351eb3..50c0c0b3e5 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -43,6 +43,7 @@ config CPU_SPECIFIC_OPTIONS
select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
select FSPS_HAS_ARCH_UPD
select GENERIC_GPIO_LIB
+ select HAVE_DEBUG_RAM_SETUP
select HAVE_FSP_GOP
select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SMI_HANDLER
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 8959bf7d46..0eeaabde69 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -312,6 +312,9 @@ static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg,
static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg,
const struct soc_intel_alderlake_config *config)
{
+ /* Set MRC debug level */
+ m_cfg->SerialDebugMrcLevel = fsp_map_console_log_level();
+
/* Set debug probe type */
m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT;