diff options
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 40 |
1 files changed, 15 insertions, 25 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 08dd6752d6..0c92c4bd7d 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -341,13 +341,6 @@ static void ich7_setup_dmi_rcrb(void) RCBA32(V0CTL) = 0x80000001; RCBA32(V1CAP) = 0x03128010; - RCBA32(ESD) = 0x00000810; - RCBA32(RP1D) = 0x01000003; - RCBA32(RP2D) = 0x02000002; - RCBA32(RP3D) = 0x03000002; - RCBA32(RP4D) = 0x04000002; - RCBA32(HDD) = 0x0f000003; - RCBA32(RP5D) = 0x05000002; pci_write_config16(PCI_DEV(0, 0x1c, 0), 0x42, 0x0141); pci_write_config16(PCI_DEV(0, 0x1c, 4), 0x42, 0x0141); @@ -361,20 +354,6 @@ static void ich7_setup_dmi_rcrb(void) reg32 |= (0x40 << 1) | (4 << 17) | (1 << 24) | (1 << 31); RCBA32(V1CTL) = reg32; - RCBA32(ESD) |= (2 << 16); - - RCBA32(ULD) |= (1 << 24) | (1 << 16); - - RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR; - - RCBA32(RP1D) |= (2 << 16); - RCBA32(RP2D) |= (2 << 16); - RCBA32(RP3D) |= (2 << 16); - RCBA32(RP4D) |= (2 << 16); - RCBA32(HDD) |= (2 << 16); - RCBA32(RP5D) |= (2 << 16); - RCBA32(RP6D) |= (2 << 16); - RCBA32(LCAP) |= (3 << 10); } @@ -871,10 +850,21 @@ static void i945_setup_root_complex_topology(void) static void ich7_setup_root_complex_topology(void) { - RCBA32(0x104) = 0x00000802; - RCBA32(0x110) = 0x00000001; - RCBA32(0x114) = 0x00000000; - RCBA32(0x118) = 0x00000000; + /* Write the R/WO registers */ + + RCBA32(ESD) |= (2 << 16); + + RCBA32(ULD) |= (1 << 24) | (1 << 16); + + RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR; + /* Write ESD.CID to TCID */ + RCBA32(RP1D) |= (2 << 16); + RCBA32(RP2D) |= (2 << 16); + RCBA32(RP3D) |= (2 << 16); + RCBA32(RP4D) |= (2 << 16); + RCBA32(HDD) |= (2 << 16); + RCBA32(RP5D) |= (2 << 16); + RCBA32(RP6D) |= (2 << 16); } static void ich7_setup_pci_express(void) |