diff options
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 49 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 31 |
2 files changed, 80 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index b9be02bf1d..47f6d59bc6 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -438,6 +438,55 @@ struct soc_intel_alderlake_config { struct vr_config domain_vr_config[NUM_VR_DOMAINS]; uint16_t MaxDramSpeed; + + enum { + SLP_S3_ASSERTION_DEFAULT, + SLP_S3_ASSERTION_60_US, + SLP_S3_ASSERTION_1_MS, + SLP_S3_ASSERTION_50_MS, + SLP_S3_ASSERTION_2_S, + } pch_slp_s3_min_assertion_width; + + enum { + SLP_S4_ASSERTION_DEFAULT, + SLP_S4_ASSERTION_1S, + SLP_S4_ASSERTION_2S, + SLP_S4_ASSERTION_3S, + SLP_S4_ASSERTION_4S, + } pch_slp_s4_min_assertion_width; + + enum { + SLP_SUS_ASSERTION_DEFAULT, + SLP_SUS_ASSERTION_0_MS, + SLP_SUS_ASSERTION_500_MS, + SLP_SUS_ASSERTION_1_S, + SLP_SUS_ASSERTION_4_S, + } pch_slp_sus_min_assertion_width; + + enum { + SLP_A_ASSERTION_DEFAULT, + SLP_A_ASSERTION_0_MS, + SLP_A_ASSERTION_4_S, + SLP_A_ASSERTION_98_MS, + SLP_A_ASSERTION_2_S, + } pch_slp_a_min_assertion_width; + + /* + * PCH PM Reset Power Cycle Duration + * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the + * stretch duration programmed in the following registers: + * - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) + * - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) + * - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) + * - PM_CFG.SLP_LAN_MIN_ASST_WDTH + */ + enum { + POWER_CYCLE_DURATION_DEFAULT, + POWER_CYCLE_DURATION_1S, + POWER_CYCLE_DURATION_2S, + POWER_CYCLE_DURATION_3S, + POWER_CYCLE_DURATION_4S, + } pch_reset_power_cycle_duration; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 584364b81e..a92883cb50 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -13,6 +13,7 @@ #include <option.h> #include <intelblocks/irq.h> #include <intelblocks/lpss.h> +#include <intelblocks/pmclib.h> #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> #include <intelblocks/tcss.h> @@ -618,6 +619,36 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, fill_vr_domain_config(s_cfg, i, &config->domain_vr_config[i]); s_cfg->LpmStateEnableMask = get_supported_lpm_mask(); + + /* Apply minimum assertion width settings */ + if (config->pch_slp_s3_min_assertion_width == SLP_S3_ASSERTION_DEFAULT) + s_cfg->PchPmSlpS3MinAssert = SLP_S3_ASSERTION_50_MS; + else + s_cfg->PchPmSlpS3MinAssert = config->pch_slp_s3_min_assertion_width; + + if (config->pch_slp_s4_min_assertion_width == SLP_S4_ASSERTION_DEFAULT) + s_cfg->PchPmSlpS4MinAssert = SLP_S4_ASSERTION_1S; + else + s_cfg->PchPmSlpS4MinAssert = config->pch_slp_s4_min_assertion_width; + + if (config->pch_slp_sus_min_assertion_width == SLP_SUS_ASSERTION_DEFAULT) + s_cfg->PchPmSlpSusMinAssert = SLP_SUS_ASSERTION_4_S; + else + s_cfg->PchPmSlpSusMinAssert = config->pch_slp_sus_min_assertion_width; + + if (config->pch_slp_a_min_assertion_width == SLP_A_ASSERTION_DEFAULT) + s_cfg->PchPmSlpAMinAssert = SLP_A_ASSERTION_2_S; + else + s_cfg->PchPmSlpAMinAssert = config->pch_slp_a_min_assertion_width; + + unsigned int power_cycle_duration = config->pch_reset_power_cycle_duration; + if (power_cycle_duration == POWER_CYCLE_DURATION_DEFAULT) + power_cycle_duration = POWER_CYCLE_DURATION_4S; + + s_cfg->PchPmPwrCycDur = get_pm_pwr_cyc_dur(s_cfg->PchPmSlpS4MinAssert, + s_cfg->PchPmSlpS3MinAssert, + s_cfg->PchPmSlpAMinAssert, + power_cycle_duration); } static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, |