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-rw-r--r--src/include/spd_bin.h6
-rw-r--r--src/lib/spd_bin.c148
-rw-r--r--src/mainboard/google/cyan/spd/spd.c6
3 files changed, 127 insertions, 33 deletions
diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h
index e0a50ff45b..3de60a95ce 100644
--- a/src/include/spd_bin.h
+++ b/src/include/spd_bin.h
@@ -31,8 +31,10 @@
#define SPD_DRAM_DDR4 0x0C
#define SPD_DENSITY_BANKS 4
#define SPD_ADDRESSING 5
-#define SPD_ORGANIZATION 7
-#define SPD_BUS_DEV_WIDTH 8
+#define DDR3_ORGANIZATION 7
+#define DDR3_BUS_DEV_WIDTH 8
+#define DDR4_ORGANIZATION 12
+#define DDR4_BUS_DEV_WIDTH 13
#define DDR3_SPD_PART_OFF 128
#define DDR3_SPD_PART_LEN 18
#define LPDDR3_SPD_PART_OFF 128
diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c
index 1598ff162f..62e600b2c8 100644
--- a/src/lib/spd_bin.c
+++ b/src/lib/spd_bin.c
@@ -33,54 +33,146 @@ void dump_spd_info(struct spd_block *blk)
}
}
-void print_spd_info(uint8_t spd[])
+static bool is_memory_type_ddr4(int dram_type)
{
- const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
- const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 128 };
- const int spd_rows[8] = {12, 13, 14, 15, 16, 17, -1, -1 };
- const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
- const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
- const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
- const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
- char spd_name[DDR4_SPD_PART_LEN+1] = { 0 };
+ return (dram_type == SPD_DRAM_DDR4);
+}
- int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
- int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
- int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
- int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
- int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
- int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
- int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
+static const char *spd_get_module_type_string(int dram_type)
+{
+ switch (dram_type) {
+ case SPD_DRAM_DDR3:
+ return "DDR3";
+ case SPD_DRAM_LPDDR3_INTEL:
+ case SPD_DRAM_LPDDR3_JEDEC:
+ return "LPDDR3";
+ case SPD_DRAM_DDR4:
+ return "DDR4";
+ }
+ return "UNKNOWN";
+}
- /* Module type */
- printk(BIOS_INFO, "SPD: module type is ");
- switch (spd[SPD_DRAM_TYPE]) {
+static int spd_get_banks(const uint8_t spd[], int dram_type)
+{
+ static const int ddr3_banks[4] = { 8, 16, 32, 64 };
+ static const int ddr4_banks[10] = { 4, 8, -1, -1, 8, 16, -1, -1, 16, 32 };
+ int index = (spd[SPD_DENSITY_BANKS] >> 4) & 0xf;
+ switch (dram_type) {
+ /* DDR3 and LPDDR3 has the same bank definition */
+ case SPD_DRAM_DDR3:
+ case SPD_DRAM_LPDDR3_INTEL:
+ case SPD_DRAM_LPDDR3_JEDEC:
+ if (index >= ARRAY_SIZE(ddr3_banks))
+ return -1;
+ return ddr3_banks[index];
+ case SPD_DRAM_DDR4:
+ if (index >= ARRAY_SIZE(ddr4_banks))
+ return -1;
+ return ddr4_banks[index];
+ default:
+ return -1;
+ }
+}
+
+static int spd_get_capmb(const uint8_t spd[])
+{
+ static const int spd_capmb[10] = { 1, 2, 4, 8, 16, 32, 64, 128, 48, 96 };
+ int index = spd[SPD_DENSITY_BANKS] & 0xf;
+ if (index >= ARRAY_SIZE(spd_capmb))
+ return -1;
+ return spd_capmb[index] * 256;
+}
+
+static int spd_get_rows(const uint8_t spd[])
+{
+ static const int spd_rows[7] = { 12, 13, 14, 15, 16, 17, 18 };
+ int index = (spd[SPD_ADDRESSING] >> 3) & 7;
+ if (index >= ARRAY_SIZE(spd_rows))
+ return -1;
+ return spd_rows[index];
+}
+
+static int spd_get_cols(const uint8_t spd[])
+{
+ static const int spd_cols[4] = { 9, 10, 11, 12 };
+ int index = spd[SPD_ADDRESSING] & 7;
+ if (index >= ARRAY_SIZE(spd_cols))
+ return -1;
+ return spd_cols[index];
+}
+
+static int spd_get_ranks(const uint8_t spd[], int dram_type)
+{
+ static const int spd_ranks[8] = { 1, 2, 3, 4, 5, 6, 7, 8 };
+ int organ_offset = is_memory_type_ddr4(dram_type) ? DDR4_ORGANIZATION
+ : DDR3_ORGANIZATION;
+ int index = (spd[organ_offset] >> 3) & 7;
+ if (index >= ARRAY_SIZE(spd_ranks))
+ return -1;
+ return spd_ranks[index];
+}
+
+static int spd_get_devw(const uint8_t spd[], int dram_type)
+{
+ static const int spd_devw[4] = { 4, 8, 16, 32 };
+ int organ_offset = is_memory_type_ddr4(dram_type) ? DDR4_ORGANIZATION
+ : DDR3_ORGANIZATION;
+ int index = spd[organ_offset] & 7;
+ if (index >= ARRAY_SIZE(spd_devw))
+ return -1;
+ return spd_devw[index];
+}
+
+static int spd_get_busw(const uint8_t spd[], int dram_type)
+{
+ static const int spd_busw[4] = { 8, 16, 32, 64 };
+ int busw_offset = is_memory_type_ddr4(dram_type) ? DDR4_BUS_DEV_WIDTH
+ : DDR3_BUS_DEV_WIDTH;
+ int index = spd[busw_offset] & 7;
+ if (index >= ARRAY_SIZE(spd_busw))
+ return -1;
+ return spd_busw[index];
+}
+
+static void spd_get_name(const uint8_t spd[], char spd_name[], int dram_type)
+{
+ switch (dram_type) {
case SPD_DRAM_DDR3:
- printk(BIOS_INFO, "DDR3\n");
- /* Module Part Number */
memcpy(spd_name, &spd[DDR3_SPD_PART_OFF], DDR3_SPD_PART_LEN);
spd_name[DDR3_SPD_PART_LEN] = 0;
break;
case SPD_DRAM_LPDDR3_INTEL:
case SPD_DRAM_LPDDR3_JEDEC:
- printk(BIOS_INFO, "LPDDR3\n");
- /* Module Part Number */
memcpy(spd_name, &spd[LPDDR3_SPD_PART_OFF],
LPDDR3_SPD_PART_LEN);
spd_name[LPDDR3_SPD_PART_LEN] = 0;
break;
case SPD_DRAM_DDR4:
- printk(BIOS_INFO, "DDR4\n");
memcpy(spd_name, &spd[DDR4_SPD_PART_OFF], DDR4_SPD_PART_LEN);
spd_name[DDR4_SPD_PART_LEN] = 0;
- ranks = (spd[SPD_ORGANIZATION] >> 3) & 7;
- devw = spd_devw[spd[12] & 7];
- busw = spd_busw[spd[13] & 7];
break;
default:
- printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
break;
}
+}
+
+void print_spd_info(uint8_t spd[])
+{
+ char spd_name[DDR4_SPD_PART_LEN+1] = { 0 };
+ int type = spd[SPD_DRAM_TYPE];
+ int banks = spd_get_banks(spd, type);
+ int capmb = spd_get_capmb(spd);
+ int rows = spd_get_rows(spd);
+ int cols = spd_get_cols(spd);
+ int ranks = spd_get_ranks(spd, type);
+ int devw = spd_get_devw(spd, type);
+ int busw = spd_get_busw(spd, type);
+
+ /* Module type */
+ printk(BIOS_INFO, "SPD: module type is %s\n",
+ spd_get_module_type_string(type));
+ /* Module Part Number */
+ spd_get_name(spd, spd_name, type);
printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c
index 7c66e947fc..f73b9e6539 100644
--- a/src/mainboard/google/cyan/spd/spd.c
+++ b/src/mainboard/google/cyan/spd/spd.c
@@ -122,9 +122,9 @@ static void set_dimm_info(const uint8_t *spd, struct dimm_info *dimm)
const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
- int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
- int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
- int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
+ int ranks = spd_ranks[(spd[DDR3_ORGANIZATION] >> 3) & 7];
+ int devw = spd_devw[spd[DDR3_ORGANIZATION] & 7];
+ int busw = spd_busw[spd[DDR3_BUS_DEV_WIDTH] & 7];
void *hob_list_ptr;
EFI_HOB_GUID_TYPE *hob_ptr;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 10:04:57 +0000