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-rw-r--r--src/acpi/dsdt_top.asl23
-rw-r--r--src/northbridge/intel/gm45/acpi/gm45.asl1
-rw-r--r--src/northbridge/intel/haswell/acpi/hostbridge.asl1
-rw-r--r--src/northbridge/intel/i945/acpi/i945.asl2
-rw-r--r--src/northbridge/intel/ironlake/acpi/ironlake.asl1
-rw-r--r--src/northbridge/intel/pineview/acpi/pineview.asl1
-rw-r--r--src/northbridge/intel/sandybridge/acpi/sandybridge.asl7
-rw-r--r--src/northbridge/intel/x4x/acpi/x4x.asl1
-rw-r--r--src/soc/intel/apollolake/acpi/northbridge.asl5
-rw-r--r--src/soc/intel/baytrail/acpi/southcluster.asl1
-rw-r--r--src/soc/intel/braswell/acpi/southcluster.asl1
-rw-r--r--src/soc/intel/common/block/acpi/acpi/northbridge.asl11
-rw-r--r--src/soc/intel/denverton_ns/acpi/northcluster.asl2
-rw-r--r--src/soc/intel/skylake/acpi/systemagent.asl11
14 files changed, 23 insertions, 45 deletions
diff --git a/src/acpi/dsdt_top.asl b/src/acpi/dsdt_top.asl
index 0dd2002ddc..6a0129fd7b 100644
--- a/src/acpi/dsdt_top.asl
+++ b/src/acpi/dsdt_top.asl
@@ -40,5 +40,28 @@ Scope(\_SB) {
/* PCIe Configuration Space */
OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */
+
+ /* From the Linux documentation (Documentation/PCI/acpi-info.rst):
+ * [6] PCI Firmware 3.2, sec 4.1.2:
+ * If the operating system does not natively comprehend reserving the
+ * MMCFG region, the MMCFG region must be reserved by firmware. The
+ * address range reported in the MCFG table or by _CBA method (see Section
+ * 4.1.3) must be reserved by declaring a motherboard resource. For most
+ * systems, the motherboard resource would appear at the root of the ACPI
+ * namespace (under \_SB) in a node with a _HID of EISAID (PNP0C02), and
+ * the resources in this case should not be claimed in the root PCI bus's
+ * _CRS. The resources can optionally be returned in Int15 E820 or
+ * EFIGetMemoryMap as reserved memory but must always be reported through
+ * ACPI as a motherboard resource.
+ */
+ Device (PERC) // PCI ECAM Resource Consumption
+ {
+ Name (_HID, EisaId("PNP0C02"))
+ Name (_CRS, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS,
+ CONFIG_ECAM_MMCONF_LENGTH)
+ })
+ }
}
#endif
diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl
index c4636beb3e..4e86092092 100644
--- a/src/northbridge/intel/gm45/acpi/gm45.asl
+++ b/src/northbridge/intel/gm45/acpi/gm45.asl
@@ -16,7 +16,6 @@ Device (PDRC)
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
- Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl
index 513e960a09..3ecc5b3b36 100644
--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl
+++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl
@@ -178,7 +178,6 @@ Device (PDRC)
Memory32Fixed (ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, MCH_BASE_SIZE)
Memory32Fixed (ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, DMI_BASE_SIZE)
Memory32Fixed (ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, EP_BASE_SIZE)
- Memory32Fixed (ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // TXT
Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // TPM
Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl
index f935b716f6..7573e98b95 100644
--- a/src/northbridge/intel/i945/acpi/i945.asl
+++ b/src/northbridge/intel/i945/acpi/i945.asl
@@ -31,7 +31,6 @@ Device (PDRC)
// Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR
// Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR
// Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR
- // Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR
// Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH
//})
@@ -40,7 +39,6 @@ Device (PDRC)
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
- Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
diff --git a/src/northbridge/intel/ironlake/acpi/ironlake.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl
index b4bd8e9f52..f64ded4415 100644
--- a/src/northbridge/intel/ironlake/acpi/ironlake.asl
+++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl
@@ -14,7 +14,6 @@ Device (PDRC)
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00008000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
- Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl
index 4901c2195a..ab7bbcd7f7 100644
--- a/src/northbridge/intel/pineview/acpi/pineview.asl
+++ b/src/northbridge/intel/pineview/acpi/pineview.asl
@@ -15,7 +15,6 @@ Device (PDRC)
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
- Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) /* Misc ICH */
diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
index cf1d61ce9f..f269bf408c 100644
--- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
+++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
@@ -15,7 +15,6 @@ Device (PDRC)
Memory32Fixed(ReadWrite, 0, 0x00008000, MCHB)
Memory32Fixed(ReadWrite, 0, 0x00001000, DMIB)
Memory32Fixed(ReadWrite, 0, 0x00001000, EGPB)
- Memory32Fixed(ReadWrite, 0, 0x04000000, PCIX)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // TPM TIS
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
@@ -37,12 +36,6 @@ Device (PDRC)
CreateDwordField (PDRS, ^EGPB._BAS, EBR0)
EBR0 = \_SB.PCI0.MCHC.EPBR << 12
- CreateDwordField (PDRS, ^PCIX._BAS, XBR0)
- XBR0 = \_SB.PCI0.MCHC.PXBR << 26
-
- CreateDwordField (PDRS, ^PCIX._LEN, XSZ0)
- XSZ0 = 0x10000000 >> \_SB.PCI0.MCHC.PXSZ
-
Return(PDRS)
}
}
diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl
index 462cdf9661..5425867cd7 100644
--- a/src/northbridge/intel/x4x/acpi/x4x.asl
+++ b/src/northbridge/intel/x4x/acpi/x4x.asl
@@ -13,7 +13,6 @@ Device (PDRC)
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
- Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl
index 1b47509094..a304331f1d 100644
--- a/src/soc/intel/apollolake/acpi/northbridge.asl
+++ b/src/soc/intel/apollolake/acpi/northbridge.asl
@@ -116,11 +116,6 @@ Device (PDRC) /* PCI Device Resource Consumption */
{
Name (BUF0, ResourceTemplate ()
{
- /* PCI Express BAR */
- Memory32Fixed (ReadWrite,
- CONFIG_ECAM_MMCONF_BASE_ADDRESS,
- CONFIG_ECAM_MMCONF_LENGTH, PCIX)
-
/* Local APIC range (0xfee0_0000 to 0xfeef_ffff) */
Memory32Fixed (ReadOnly, 0x0fee00000, 0x00010000, LIOH)
})
diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl
index dacdd29e06..131825e341 100644
--- a/src/soc/intel/baytrail/acpi/southcluster.asl
+++ b/src/soc/intel/baytrail/acpi/southcluster.asl
@@ -189,7 +189,6 @@ Device (PDRC)
Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
- Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl
index 3dcc6c1951..1e52df171f 100644
--- a/src/soc/intel/braswell/acpi/southcluster.asl
+++ b/src/soc/intel/braswell/acpi/southcluster.asl
@@ -188,7 +188,6 @@ Device (PDRC)
Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
- Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl
index d605625bc5..44c873c8e5 100644
--- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl
+++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl
@@ -269,11 +269,6 @@ Device (PDRC)
*/
Memory32Fixed (ReadWrite, 0, EP_BASE_SIZE, EGPB)
- /* PCI Express BAR _BAS and _LEN will be updated in
- * _CRS below according to B0:D0:F0:Reg.60h
- */
- Memory32Fixed (ReadWrite, 0, 0, PCIX)
-
/* VTD engine memory range. */
Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE)
@@ -301,12 +296,6 @@ Device (PDRC)
CreateDwordField (BUF0, EGPB._BAS, EBR0)
EBR0 = \_SB.PCI0.GEPB ()
- CreateDwordField (BUF0, PCIX._BAS, XBR0)
- XBR0 = \_SB.PCI0.GPCB ()
-
- CreateDwordField (BUF0, PCIX._LEN, XSZ0)
- XSZ0 = \_SB.PCI0.GPCL ()
-
CreateDwordField (BUF0, FIOH._BAS, FBR0)
FBR0 = 0x100000000 - CONFIG_ROM_SIZE
diff --git a/src/soc/intel/denverton_ns/acpi/northcluster.asl b/src/soc/intel/denverton_ns/acpi/northcluster.asl
index e415dc4ea3..ce687dd384 100644
--- a/src/soc/intel/denverton_ns/acpi/northcluster.asl
+++ b/src/soc/intel/denverton_ns/acpi/northcluster.asl
@@ -121,8 +121,6 @@ Device (PDRC)
Name (_UID, 1)
Name (PDRS, ResourceTemplate() {
- // PCIEXBAR memory range
- Memory32Fixed(ReadOnly, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
// TSEG
Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, TSMB)
})
diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl
index 0e5d74f297..762c4f7bf3 100644
--- a/src/soc/intel/skylake/acpi/systemagent.asl
+++ b/src/soc/intel/skylake/acpi/systemagent.asl
@@ -287,11 +287,6 @@ Device (PDRC)
*/
Memory32Fixed (ReadWrite, 0, 0x01000, EGPB)
- /* PCI Express BAR _BAS and _LEN will be updated in
- * _CRS below according to B0:D0:F0:Reg.60h
- */
- Memory32Fixed (ReadWrite, 0, 0, PCIX)
-
/* VTD engine memory range. */
Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE)
@@ -314,12 +309,6 @@ Device (PDRC)
CreateDwordField (BUF0, EGPB._BAS, EBR0)
EBR0 = \_SB.PCI0.GEPB ()
- CreateDwordField (BUF0, PCIX._BAS, XBR0)
- XBR0 = \_SB.PCI0.GPCB ()
-
- CreateDwordField (BUF0, PCIX._LEN, XSZ0)
- XSZ0 = \_SB.PCI0.GPCL ()
-
CreateDwordField (BUF0, FIOH._BAS, FBR0)
FBR0 = 0x100000000 - CONFIG_ROM_SIZE
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-22 12:26:35 +0000