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-rw-r--r--src/soc/amd/cezanne/Makefile.inc1
-rw-r--r--src/soc/amd/cezanne/cpu.c1
-rw-r--r--src/soc/amd/cezanne/include/soc/cpu.h2
-rw-r--r--src/soc/amd/cezanne/mca.c14
4 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index fa38cc3785..d68a6b6290 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -39,6 +39,7 @@ ramstage-y += data_fabric.c
ramstage-y += fch.c
ramstage-y += fsp_s_params.c
ramstage-y += gpio.c
+ramstage-y += mca.c
ramstage-y += reset.c
ramstage-y += root_complex.c
ramstage-y += uart.c
diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c
index ddc49a957c..5f0a5a1a2a 100644
--- a/src/soc/amd/cezanne/cpu.c
+++ b/src/soc/amd/cezanne/cpu.c
@@ -59,6 +59,7 @@ void mp_init_cpus(struct bus *cpu_bus)
static void zen_2_3_init(struct device *dev)
{
+ check_mca();
setup_lapic();
set_cstate_io_addr();
diff --git a/src/soc/amd/cezanne/include/soc/cpu.h b/src/soc/amd/cezanne/include/soc/cpu.h
index 27647adbd1..ec83349a11 100644
--- a/src/soc/amd/cezanne/include/soc/cpu.h
+++ b/src/soc/amd/cezanne/include/soc/cpu.h
@@ -5,4 +5,6 @@
#define CEZANNE_A0_CPUID 0x00a50f00
+void check_mca(void);
+
#endif /* AMD_CEZANNE_CPU_H */
diff --git a/src/soc/amd/cezanne/mca.c b/src/soc/amd/cezanne/mca.c
new file mode 100644
index 0000000000..7160256539
--- /dev/null
+++ b/src/soc/amd/cezanne/mca.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/msr.h>
+#include <soc/cpu.h>
+
+/* Check the Machine Check Architecture Extension registers */
+void check_mca(void)
+{
+ /* TODO: Implement MCAX register checking and BERT table generation. */
+
+ /* mca_clear_status uses the MCA registers and not the MCAX ones. Since they are
+ aliases, we can use either set of registers. */
+ mca_clear_status();
+}