diff options
| -rw-r--r-- | src/mainboard/kontron/bsl6/romstage.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/skylake/romstage/fsp_params.c | 3 |
2 files changed, 2 insertions, 4 deletions
diff --git a/src/mainboard/kontron/bsl6/romstage.c b/src/mainboard/kontron/bsl6/romstage.c index b77073ca96..3206f53079 100644 --- a/src/mainboard/kontron/bsl6/romstage.c +++ b/src/mainboard/kontron/bsl6/romstage.c @@ -39,8 +39,5 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) memory_params->DqPinsInterleaved = true; memory_params->CaVrefConfig = 2; - const uint8_t ht = get_uint_option("hyper_threading", memory_params->HyperThreading); - memory_params->HyperThreading = ht; - variant_memory_init_params(mupd); } diff --git a/src/soc/intel/skylake/romstage/fsp_params.c b/src/soc/intel/skylake/romstage/fsp_params.c index d7e1157376..f24054a6b7 100644 --- a/src/soc/intel/skylake/romstage/fsp_params.c +++ b/src/soc/intel/skylake/romstage/fsp_params.c @@ -4,6 +4,7 @@ #include <cpu/x86/msr.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> +#include <option.h> #include <soc/iomap.h> #include <soc/msr.h> #include <soc/pci_devs.h> @@ -101,7 +102,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* HPET BDF already handled in coreboot code, so tell FSP to ignore UPDs */ m_cfg->PchHpetBdfValid = 0; - m_cfg->HyperThreading = CONFIG(FSP_HYPERTHREADING); + m_cfg->HyperThreading = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING)); } static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg, |