diff options
4 files changed, 46 insertions, 11 deletions
diff --git a/src/mainboard/google/brya/variants/glassway/fw_config.c b/src/mainboard/google/brya/variants/glassway/fw_config.c index 3cca3fe4c0..8ed6ea6233 100644 --- a/src/mainboard/google/brya/variants/glassway/fw_config.c +++ b/src/mainboard/google/brya/variants/glassway/fw_config.c @@ -5,6 +5,15 @@ #include <console/console.h> #include <fw_config.h> +static const struct pad_config hdmi_disable_pads[] = { + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG), + /* E21 : DDP2_CTRLDATA ==> NC */ + PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG), +}; + static const struct pad_config lte_disable_pads[] = { /* A8 : WWAN_RF_DISABLE_ODL */ PAD_NC(GPP_A8, NONE), @@ -27,8 +36,16 @@ static const struct pad_config stylus_disable_pads[] = { void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { - if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { - printk(BIOS_INFO, "Disable LTE-related GPIO pins on Glassway serial projects.\n"); + if (!fw_config_probe(FW_CONFIG(DB_USB, DB_HDMI_LTE))) { + printk(BIOS_INFO, "Disable HDMI GPIO pins.\n"); + gpio_padbased_override(padbased_table, hdmi_disable_pads, + ARRAY_SIZE(hdmi_disable_pads)); + } + + /* Set to Disable LTE-related GPIO pins when field DB_USB is not DB_1C_LTE and DB_HDMI_LTE. */ + if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE)) + && !fw_config_probe(FW_CONFIG(DB_USB, DB_HDMI_LTE))) { + printk(BIOS_INFO, "Disable LTE GPIO pins.\n"); gpio_padbased_override(padbased_table, lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); } diff --git a/src/mainboard/google/brya/variants/glassway/gpio.c b/src/mainboard/google/brya/variants/glassway/gpio.c index f9e5c417cf..c2b8f70e70 100644 --- a/src/mainboard/google/brya/variants/glassway/gpio.c +++ b/src/mainboard/google/brya/variants/glassway/gpio.c @@ -8,8 +8,6 @@ static const struct pad_config override_gpio_table[] = { /* A8 : WWAN_RF_DISABLE_ODL */ PAD_CFG_GPO(GPP_A8, 1, DEEP), - /* A20 : DDSP_HPD2 ==> NC */ - PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG), /* D3 : ISH_GP3 ==> NC */ PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), /* D6 : WWAN_EN */ @@ -26,10 +24,6 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_GPI(GPP_E4, NONE, DEEP), /* E5 : SDD_STRAP2 */ PAD_CFG_GPI(GPP_E5, NONE, DEEP), - /* E20 : DDP2_CTRLCLK ==> NC */ - PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG), - /* E21 : DDP2_CTRLDATA ==> NC */ - PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG), /* F12 : WWAN_RST_L */ PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), /* H19 : SOC_I2C_SUB_INT_ODL */ diff --git a/src/mainboard/google/brya/variants/glassway/overridetree.cb b/src/mainboard/google/brya/variants/glassway/overridetree.cb index b8751c703f..7a12c29f4c 100644 --- a/src/mainboard/google/brya/variants/glassway/overridetree.cb +++ b/src/mainboard/google/brya/variants/glassway/overridetree.cb @@ -13,6 +13,7 @@ fw_config option DB_1A 2 option DB_1C_1A 3 option DB_1C_LTE 4 + option DB_HDMI_LTE 5 end field SD_CARD 8 option SD_ABSENT 0 @@ -496,6 +497,7 @@ chip soc/intel/alderlake register "input_analog_gain" = "1" device i2c 28 on probe DB_USB DB_1C_LTE + probe DB_USB DB_HDMI_LTE end end end #I2C2 @@ -612,7 +614,12 @@ chip soc/intel/alderlake chip drivers/intel/pmc_mux/conn use usb2_port2 as usb2_port use tcss_usb3_port2 as usb3_port - device generic 1 alias conn1 on end + device generic 1 alias conn1 on + probe DB_USB DB_1C + probe DB_USB DB_1A + probe DB_USB DB_1C_1A + probe DB_USB DB_1C_LTE + end end end end @@ -632,7 +639,11 @@ chip soc/intel/alderlake register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" - device ref tcss_usb3_port2 on end + device ref tcss_usb3_port2 on + probe DB_USB DB_1C + probe DB_USB DB_1C_1A + probe DB_USB DB_1C_LTE + end end end end @@ -652,7 +663,11 @@ chip soc/intel/alderlake register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" - device ref usb2_port2 on end + device ref usb2_port2 on + probe DB_USB DB_1C + probe DB_USB DB_1C_1A + probe DB_USB DB_1C_LTE + end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A0 (MLB)"" @@ -667,6 +682,7 @@ chip soc/intel/alderlake register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" device ref usb2_port4 on + probe DB_USB DB_1A probe DB_USB DB_1C_1A end end @@ -675,6 +691,7 @@ chip soc/intel/alderlake register "type" = "UPC_TYPE_INTERNAL" device ref usb2_port4 on probe DB_USB DB_1C_LTE + probe DB_USB DB_HDMI_LTE end end chip drivers/usb/acpi @@ -709,6 +726,7 @@ chip soc/intel/alderlake register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" device ref usb3_port2 on + probe DB_USB DB_1A probe DB_USB DB_1C_1A end end @@ -717,6 +735,7 @@ chip soc/intel/alderlake register "type" = "UPC_TYPE_INTERNAL" device ref usb3_port2 on probe DB_USB DB_1C_LTE + probe DB_USB DB_HDMI_LTE end end end diff --git a/src/mainboard/google/brya/variants/glassway/variant.c b/src/mainboard/google/brya/variants/glassway/variant.c index 2a4d4f112a..5058516d36 100644 --- a/src/mainboard/google/brya/variants/glassway/variant.c +++ b/src/mainboard/google/brya/variants/glassway/variant.c @@ -12,6 +12,11 @@ const char *get_wifi_sar_cbfs_filename(void) void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { + if (fw_config_probe(FW_CONFIG(DB_USB, DB_HDMI_LTE))) { + printk(BIOS_INFO, "Enable DDI PORT 2 for HPD and DDC.\n"); + config->ddi_ports_config[DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC; + } + if (!fw_config_probe(FW_CONFIG(WFC, WFC_PRESENT))) { printk(BIOS_INFO, "Disable usb2_port7 of WFC.\n"); config->usb2_ports[6].enable = 0; |